I2S Serial Bus Interface with Dynamic Word Select Synthesizer
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Solution Overview
Problem
Existing I2S serial bus interfaces are limited in supporting multiple sample rates, as they often require high-frequency clock signals, leading to undesirably long audio frames and unused bits, and cannot generate WS signals with non-integer multiples of the clock frequency, making it difficult to transmit and receive audio data at different sample rates efficiently.
Innovation Solution
A serial bus interface with a word select (WS) synthesizer that dynamically adjusts the periodicity of the WS signal to achieve a desired frequency, which is a non-integer multiple of the clock frequency, using direct digital synthesis and feedback loops to regulate the effective frequency, allowing for the generation of WS signals such as 44.1 kHz and 48 kHz from a single 6.144 MHz clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used to generate WS signals for multiple sample rates, then device complexity is reduced, but manufacturing precision of WS signal frequency is worsened when the clock frequency is a non-integer multiple of the desired WS frequency
Solution Approach 1:
The patent employs a feedback mechanism where the WS synthesizer continuously monitors the actual WS signal frequency and dynamically adjusts its internal timing parameters to compensate for the non-integer multiple relationship between the clock frequency and desired WS frequency. This feedback loop ensures that the WS signal maintains precise frequency accuracy (within 0.1% error) even when derived from a single clock signal that is not an integer multiple of the target frequency.
Solution Approach 2:
The WS synthesizer dynamically changes its internal timing parameters and periodicity based on the detected frequency error. By adjusting parameters such as the number of clock cycles per WS period and the phase alignment, the system adapts to maintain accurate WS signal frequency despite the non-integer multiple constraint, enabling precise support for both 44.1 kHz and 48 kHz sample rates from a 6.144 MHz clock.
2Adaptability or versatility
If high-frequency clock signals are used to support multiple sample rates, then sample rate versatility is improved, but audio frame length increases leading to unused bits and reduced efficiency
Solution Approach 1:
The system dynamically adjusts the WS signal periodicity and frame structure based on the detected sample rate requirements. The WS synthesizer can flexibly change the number of clock cycles per WS period and the timing of WS transitions to match the desired sample rate (44.1 kHz or 48 kHz), ensuring that audio frames are optimally filled without excessive unused bits, thereby improving transmission efficiency while maintaining versatility.
Solution Approach 2:
The patent changes key parameters including the WS signal frequency, the number of clock cycles per audio frame, and the alignment of data bits within frames according to the selected sample rate. This parameter adaptation allows the system to minimize unused bits in audio frames for each sample rate while maintaining support for multiple rates, reducing waste and improving overall system efficiency.
3Stability of the object's composition
If the WS signal frequency is fixed as an integer multiple of the clock frequency, then signal stability is improved, but adaptability to different sample rates is reduced
Solution Approach 1:
The WS synthesizer implements dynamic periodicity adjustment where the WS signal period is not fixed but adaptively changed based on the desired sample rate. The system can switch between different periodicity configurations (corresponding to 44.1 kHz, 48 kHz, and other sample rates) while maintaining stable and precise timing within each configuration. This dynamic adaptability allows the system to support multiple sample rates without compromising signal stability during operation.
Solution Approach 2:
The WS synthesizer is designed as a universal frequency generator that can produce WS signals for multiple different sample rates using a single clock input. By implementing a multi-functional design that can dynamically reconfigure its timing parameters, the synthesizer achieves both stability (through precise frequency control) and versatility (through support for multiple sample rates), eliminating the need for separate fixed-frequency WS signal generators for each sample rate.
Data Source
AI summary
This disclosure provides methods, devices, and systems for audio communications. The present implementations more specifically relate to transmitting and receiving audio data at sample rates that are non-integer multiples of a clock frequency. In some aspects, a serial bus interface may generate a word select (WS) signal based on an input clock signal and may dynamically adjust a periodicity of the WS signal so that the WS signal has an effective frequency equal to a non-integer multiple of the clock frequency. In some implementations, the WS signal may be produced by direct digital synthesis (DDS) of the clock signal using a frequency control word (FCW). In such implementations, the periodicity of the WS signal may be dynamically adjusted by biasing the FCW based on errors or differences between the frequency of the WS signal and the desired frequency (such as in a feedback loop).