Device Transparent Grouping for I3C Bus Address Expansion
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Solution Overview
Problem
The existing MIPI I3C bus specification limits device addressing to 128 unique devices due to its 7-bit addressing scheme, which is insufficient for systems requiring more than 128 devices to be connected, such as DDR memory systems with multiple DIMMs, leading to inefficiencies and complexity in expanding the address space without redesigning the bus or adding additional controllers.
Innovation Solution
A device-transparent mechanism that dynamically slices devices into groups, using pin multiplexing and I/O routing to expand the number of addressable devices beyond the native address space of a multi-drop bus, allowing up to 256 devices to be addressed using the same 7-bit address space by swapping clock and data lines between device groups, thereby avoiding the need for additional bus instances or redesigning the bus specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the MIPI I3C bus specification with 7-bit addressing is used, then device communication is simplified and compatibility is maintained, but the number of addressable devices is limited to 128
Solution Approach 1:
The patent segments the 128 addressable devices into multiple groups (e.g., Group 0 and Group 1), where each group can be independently addressed using the original 7-bit address space. A group selection mechanism (such as a multiplexer or additional address bit) is introduced to switch between groups, effectively doubling the total addressable devices to 256 while maintaining compatibility with the original I3C specification for devices within each group.
Solution Approach 2:
The patent adds an additional dimension to the addressing scheme by introducing a group selection mechanism (such as an 8th address bit or a separate group select signal) that works in conjunction with the original 7-bit device address. This creates a two-level addressing hierarchy: group level (1 bit) and device level (7 bits), expanding the addressable space from 128 to 256 devices without changing the fundamental 7-bit addressing structure within each group.
2Adaptability or versatility
If additional bus instances or controllers are added to expand address space beyond 128 devices, then more devices can be addressed, but system complexity and cost increase
Solution Approach 1:
The patent makes the existing I3C bus controller universal by introducing a group selection mechanism that allows a single controller to manage multiple device groups (e.g., 2 groups of 128 devices). The controller can dynamically switch between groups using the additional address bit or group select signal, enabling one controller to address up to 256 devices without requiring additional bus instances or controllers, thus maintaining system simplicity while expanding addressability.
3Adaptability or versatility
If the address space is expanded beyond 128 devices, then more devices can be connected, but compatibility with the I3C specification may be compromised
Solution Approach 1:
The patent segments the expanded address space into multiple groups, where each group maintains the original 7-bit addressing scheme compatible with the I3C specification. Devices within each group are addressed using standard I3C protocols, ensuring specification compatibility. The segmentation allows the system to present multiple 128-device groups to the bus, with each group behaving as if it were a standard I3C bus, thus maintaining reliability and compatibility while achieving expansion.
Solution Approach 2:
The patent introduces an intermediary mechanism (such as a multiplexer or address decoding logic) that translates the expanded addressing requirements into standard I3C compatible addresses. When a device in a higher group is addressed, the intermediary automatically adjusts the address presentation to match the 7-bit I3C format, ensuring that the bus controller and devices interact according to the specification while still supporting beyond 128 devices through the group selection mechanism.
Data Source
AI summary
In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.