I3C Bus Time Stamping via Master-Slave Synchronization
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Solution Overview
Problem
The existing Inter-Integrated Circuit (I2C) message protocol requires additional communication lines and signal pins for simultaneous operation of multiple slave devices, leading to increased complexity and inefficiency in time stamping and triggering events.
Innovation Solution
The I3C message protocol enhances synchronization by using a common 'Time Sync' command to synchronize multiple slave devices with a master device, eliminating the need for side channels and allowing simultaneous operations through a two-wire communication link, where the master device issues a Time Sync command to synchronize local clock signals across all slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional communication lines and signal pins are used for time stamping and triggering in I2C protocol, then simultaneous operation of multiple slave devices is enabled, but device complexity and board trace requirements increase
Solution Approach 1:
The patent combines the time stamping and triggering functions into the existing I2C communication protocol by utilizing the SDA and SCL lines. The master device embeds time stamp information and trigger commands within standard I2C data packets, eliminating the need for separate communication channels. This merging approach allows multiple slave devices to operate simultaneously while reusing the same physical bus infrastructure.
Solution Approach 2:
The I2C bus lines (SDA and SCL) are made multi-functional by enabling them to carry both data communication and timing synchronization functions. The master device uses the same bus to transmit data, issue trigger commands, and provide time stamp information to multiple slave devices. This universal usage of the existing bus reduces the need for additional dedicated lines for timing and triggering operations.
2Measurement precision
If dedicated feedback lines are provided for each slave device to signal event timing, then accurate time stamping is achieved, but the number of communication lines and signal pins increases
Solution Approach 1:
The master device acts as an intermediary that centralizes the time stamping function. Instead of each slave device having a dedicated feedback line to signal event timing, the slave devices report their event timing information back to the master device through the shared I2C bus. The master device then correlates these reports with its own time base to achieve accurate time stamping. This intermediary approach maintains timing accuracy while using the shared bus infrastructure.
Solution Approach 2:
The patent uses the existing I2C data communication channel to copy the timing information that would otherwise require dedicated feedback lines. Slave devices transmit their event timing data through the standard I2C data packets, effectively copying the timing signal function onto the existing communication infrastructure. This eliminates the need for separate physical timing feedback lines for each slave device.
3Productivity
If I2C protocol is used for peripheral device communication, then low-speed operation is sufficient for sensors and gyroscopes, but synchronization efficiency and speed are limited
Solution Approach 1:
The master device performs preliminary synchronization actions by issuing time stamp commands and trigger instructions before the actual measurement operations. Multiple slave devices receive and buffer these timing commands in advance, allowing them to synchronize their operations without requiring high-speed continuous communication. This preliminary action approach improves synchronization efficiency by decoupling the timing command transmission from the actual data acquisition speed.
Data Source
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AI summary
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.