Deadlock Solver Interface for I3C Hot-Join Reset Exit

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Solution Overview

Problem

The I3C protocol's Hot-Join mechanism can fail when a slave device attempts to join an I3C bus with a master controller in sleep mode, causing a 'hot-join deadlock due to the slave controller's inability to synchronize its clock, leading to power inefficiencies in existing solutions.

Innovation Solution

A deadlock solver provides a communication interface between the master and slave controllers, mimicking a transaction to assist the slave controller in completing its reset pattern, even when the master controller's clock is idle, using on-chip signals to ensure synchronization and prevent hardware glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the master controller's clock is idle during bus initialization, then the slave device cannot complete its reset pattern and exit reset state, but introducing a deadlock solver with signal pattern transmission increases device complexity

Engineering Contradiction:
Improveslave device reset completionVSAvoiddeadlock solver architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a deadlock solver as an intermediary component between the master controller and slave device. This mediator detects reset event indicators and generates appropriate signal patterns (START, DATA, STOP conditions) to simulate master controller transactions, enabling the slave device to complete its reset pattern even when the actual master clock is idle. The deadlock solver acts as a temporary substitute master during reset operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The deadlock solver performs preliminary actions by pre-generating and transmitting the necessary signal patterns before the slave device can complete its reset. The system detects the reset event indicator in advance and proactively provides the required clock cycles and transaction signals, rather than waiting for the master controller to become active.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the master controller periodically wakes up to check for slave devices, then the system can detect reset events, but this periodic waking consumes excessive energy

Engineering Contradiction:
Improvereset event detectionVSAvoidmaster controller power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The slave device performs self-service by autonomously detecting its own reset event indicator and generating the necessary signal patterns through the deadlock solver without requiring the master controller to wake up and poll for its presence. The system transitions from master-initiated periodic checking to slave-initiated self-detection and self-service.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback by monitoring the reset event indicator generated by the slave device itself. This feedback mechanism allows the deadlock solver to detect when a slave needs assistance and automatically provide the appropriate signal patterns, eliminating the need for continuous master controller polling.

Inventive Principle:
Principle #23Feedback

3Ease of operation

If the deadlock solver transmits signal patterns to assist slave controller, then the slave device can exit reset state successfully, but the communication interface complexity increases

Engineering Contradiction:
Improveslave device hot-join capabilityVSAvoidcommunication interface
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The communication interface is segmented into distinct functional components: a detection unit that monitors reset event indicators, a generation unit that creates appropriate signal patterns (START, DATA, STOP conditions), and a transmission unit that outputs these patterns through the I3C bus. This segmentation allows each component to perform its specific function independently, simplifying the overall design despite the increased capability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12613753B2Architecture to prevent controller-to-controller deadlock
Publication Date: 2026.04.28 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12613753B2 patent drawing
  • US12613753B2 patent drawing
  • US12613753B2 patent drawing

AI summary

An integrated circuit chip includes a secondary controller coupled to a deadlock solver that provides a communication interface to a primary controller. The deadlock solver stores control logic executable to detect a reset event indicator on a secondary controller that is indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state. Based at least in part on detection of the reset event indicator, the deadlock solver transmits a signal pattern to the secondary controller that mimics a transaction from a primary controller. The signal pattern assisting the secondary controller in exiting a reset state.