I3C Bus Parity Error Detection Mechanism
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Solution Overview
Problem
In the Improved Inter-Integrated Circuit (I3C) communication standard, error detection for signals without prepared error detection mechanisms can lead to difficulties in determining correct received data, causing communication failures between the master and slave devices.
Innovation Solution
A communication apparatus and method that includes a transmission/reception unit and an error detection unit, which performs parity checks assuming one bit of 2-bit parity as even parity and the other bit as odd parity to detect errors in received data, ensuring reliable communication by distinguishing between correct and incorrect data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection is performed using traditional parity methods in I3C communication, then error detection capability is provided, but reliable detection of errors in signals without prepared error detection mechanisms is difficult
Solution Approach 1:
The parity check mechanism is segmented into two independent parity bits (even parity bit and odd parity bit) that operate separately on different subsets of data bits. This segmentation allows each parity bit to detect specific error patterns independently, improving overall error detection reliability without requiring a complex unified error detection mechanism.
Solution Approach 2:
The patent introduces an intermediary error detection mechanism that uses dual parity bits as mediators between the transmitted data and the reception verification process. These parity bits act as intermediaries that carry error detection information without being part of the original data, enabling reliable error detection while maintaining communication protocol simplicity.
2Stability of the object's composition
If both master and slave devices do not drive a data signal line due to undetected errors, then communication continuity is maintained, but detection of incorrect received data becomes difficult
Solution Approach 1:
The patent implements feedback through dual parity bits that provide continuous error detection information to both master and slave devices. When data is transmitted, parity bits are calculated and transmitted along with the data. The receiving device calculates expected parity values and compares them with received parity values, providing feedback on data correctness. This feedback mechanism enables precise detection of incorrect received data while maintaining communication stability through proper error handling.
Solution Approach 2:
The patent employs asymmetric parity checking where even parity bits and odd parity bits serve different detection purposes. The even parity bit checks for errors in specific bit positions while the odd parity bit checks other positions, creating an asymmetric detection scheme that improves precision in identifying incorrect data without disrupting communication stability.
3Reliability
If 2-bit parity is used for error detection, then error detection capability is enhanced, but the complexity of performing both even and odd parity checks increases
Solution Approach 1:
The 2-bit parity system is segmented into independent even and odd parity components, each handling specific error detection tasks. This segmentation reduces processing complexity by allowing parallel independent calculation of even and odd parity bits rather than requiring complex interdependent verification logic.
Solution Approach 2:
The patent changes the parameter of parity verification by using two different parity types (even and odd) with different check criteria. This parameter change enables enhanced error detection capability through diverse verification approaches while keeping individual check procedures simple and computationally efficient.
Data Source
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AI summary
A master includes a transmission/reception unit which transmits/receives a signal to/from a slave, and an error detection unit which detects error occurrence by performing parity check to data received by the transmission/reception unit. Then, the error detection unit performs error detection assuming one bit of 2-bit parity included in the data received by the transmission/reception unit as even parity, and the other bit as odd parity. The present technology can be applied to a bus IF which performs communication in compliance with, for example, an I3C standard.