I3C Write Completion Interrupts for Efficient Bus Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The conventional I3C bus configuration requires repeated write access requests due to NACK responses, leading to reduced data transfer efficiency and bandwidth utilization, especially when multiple slaves are connected, as the bus is occupied by slaves with high write latency.
Innovation Solution
Implementing a communication method that includes transmitting access requests with NACK responses and enabling interrupt-based write completion status notifications, allowing the master to standby until a write completion status is received via interrupt requests, thereby reducing unnecessary repetitions and optimizing bus usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the I3C master repeatedly makes write access requests until ACK response is received, then the data writing reliability is ensured, but the data transfer efficiency is reduced
Solution Approach 1:
The slave device provides feedback through interrupt requests to notify the master when data writing is completed. This feedback mechanism allows the master to stop repeated access requests once writing is done, ensuring reliability while improving transfer efficiency by avoiding unnecessary repetitions.
2Reliability
If the I3C master repeatedly makes write access requests, then the data writing completion is ensured, but the bus occupancy is increased
Solution Approach 1:
The slave device sends interrupt requests as feedback to notify the master when data writing is completed. This allows the master to release the bus promptly after writing completion, ensuring data writing reliability while reducing bus occupancy time by eliminating unnecessary repeated requests.
3Reliability
If a slave with large write latency occupies the bus for repeated requests, then its data writing is completed, but the bandwidth for other slaves is limited
Solution Approach 1:
The slave device with large write latency provides interrupt feedback to notify the master when writing is completed. This allows the master to stop repeated requests and release the bus, ensuring the slave's data writing reliability while improving overall bandwidth utilization by allowing other slaves to access the bus during the write latency period.
Data Source
AI summary
The present disclosure relates to a communication apparatus, a communication method, and a program capable of improving transfer efficiency of data transfer.An I3C master transmits an access request which requests writing of data to an I3C slave, determines whether or not a write completion status in response to the access request is transmitted from the I3C slave by an interrupt request in a case where the response of the I3C slave to the access request is a NACK response, and stands by for a process until the write completion status is transmitted by the interrupt request. The I3C slave receives the access request transmitted from the I3C master, transmits a NACK response to the I3C master in a case where writing of data in response to the access request is not completed, and transmits a write completion status by an interrupt request at a timing when the writing of the data in the response to the access request has been completed. The present technology can be applied to, for example, a communication system that performs communication in accordance with the I3C standard.