I3C Write Flow Control Using Transition Bit Signaling

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Solution Overview

Problem

Current serial bus protocols, such as I3C, lack a flow control mechanism that allows slave devices to pause or stop transmissions during write transactions, leading to issues when the receiving device has insufficient resources, such as memory or processing capacity.

Innovation Solution

Implementing a transition bit (T-bit) in place of the parity bit in I3C SDR write frames, allowing slave devices to assert flow control by driving the data line to a high state and entering a high impedance mode, which causes the master device to transmit a STOP or repeated START condition, thereby terminating the transaction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the master device continuously transmits data during write transactions, then productivity is improved, but the slave device may experience resource overload due to insufficient memory or processing capacity

Engineering Contradiction:
Improvedata transmission throughputVSAvoidslave device resource management
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements flow control by allowing the slave device to monitor incoming data and send feedback signals to the master device. When the slave device's resources are sufficient, it continues receiving data. When resources are depleted, it sends a flow control signal (by driving the data line low during the T-bit interval) to request the master device to pause or terminate the transaction, preventing resource overload while maintaining high throughput during normal operation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the data transmission process dynamic by enabling the slave device to control the flow of data in real-time. The transaction can dynamically transition between continuing and pausing/terminating based on the slave device's current resource state, allowing the system to adapt to changing conditions rather than following a fixed transmission pattern

Inventive Principle:
Principle #15Dynamics

2Reliability

If the slave device monitors resources continuously to prevent overload, then reliability is improved, but the complexity of the slave device increases

Engineering Contradiction:
Improveresource overload preventionVSAvoidslave device control logic
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The slave device autonomously monitors its own resource state and independently determines when to send flow control signals. The slave device uses its existing acknowledgment mechanism and the unused T-bit interval to communicate its resource status, leveraging existing infrastructure rather than requiring complex external monitoring systems or additional control circuits

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If the transition bit is used for flow control signaling, then adaptability is improved, but the manufacturing precision requirements increase due to timing constraints

Engineering Contradiction:
Improveflow control capabilityVSAvoidbit interval timing
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent makes the T-bit field multi-functional by using it for both its original transition purpose and for flow control signaling. This reuse of existing protocol infrastructure enables flow control capability without adding separate dedicated signaling mechanisms, though it does require precise timing control to distinguish between the two functions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11023408B2I3C single data rate write flow control
Publication Date: 2021.06.01 QUALCOMM INC
  • US11023408B2 patent drawing
  • US11023408B2 patent drawing
  • US11023408B2 patent drawing

AI summary

Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described that enable a slave device to request that a bus master device terminate a write transaction with the slave device. The serial bus may be operated according to an I3C single data rate protocol. In various aspects of the disclosure, a method performed at a master device coupled to a serial bus includes initiating a write transaction between the master device and a slave device, where the write transaction includes a plurality of data frames, and at least one data frame is configured with a transition bit in place of a parity bit. The method may include terminating the write transaction when the slave device drives a data line of the serial bus while receiving the transition bit.