In-Band Error Correction Code Memory Tagging for Data Integrity
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Solution Overview
Problem
Current data protection techniques, such as out-of-band ECC memory, incur significant performance and memory overheads, making them unsuitable for production use in systems with high error tolerance requirements, whereas in-band ECC memory lacks efficient error correction mechanisms for ensuring data integrity.
Innovation Solution
The implementation of in-line or in-band error correction code (IBECC) using a memory tagging extension (MTE) on Armv9 architectures, which allocates a portion of memory to store ECC metadata, allowing for single error correction and double error detection (SECDED) with reduced capacity overhead and no pin count increase, by utilizing 4-bit memory tags and SECDED codes for data protection at 64-byte or 32-byte granularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If out-of-band ECC memory is used, then data integrity is improved, but memory overhead and performance overhead increase significantly
Solution Approach 1:
The patent merges the ECC code with the data storage space by allocating a portion of the memory address space to store ECC metadata. This integration eliminates the need for separate ECC memory chips and reduces memory overhead while maintaining data integrity protection through SECDED error correction capabilities.
Solution Approach 2:
The patent introduces memory tagging extension (MTE) that adds a tagging dimension to the memory address space. By using 4-bit memory tags associated with memory regions, the system achieves error detection and correction without requiring additional physical memory resources, thus resolving the contradiction between reliability and memory overhead.
2Reliability
If out-of-band ECC memory is used, then data integrity is improved, but performance overhead increases
Solution Approach 1:
By combining ECC metadata storage within the same memory address space as data, the patent eliminates the performance penalty associated with accessing separate ECC memory chips. The integrated approach allows parallel processing of data and ECC operations, reducing performance overhead while maintaining integrity protection.
3Device complexity
If in-band ECC memory is used, then memory overhead is reduced, but efficient error correction mechanisms are lacking
Solution Approach 1:
The patent changes the parameter of error correction capability by implementing SECDED (single error correction, double error detection) using 4-bit memory tags. This enhancement provides robust error correction mechanisms within the in-band architecture, achieving both low memory overhead and high reliability.
4Reliability
If memory tagging extension is used for IBECC, then error correction capability is improved, but memory bandwidth usage increases
Solution Approach 1:
The patent applies partial action by using only 4-bit memory tags instead of full-width ECC codes. This partial approach provides sufficient error correction capability (SECDED) while minimizing the impact on memory bandwidth, achieving a balance between reliability enhancement and bandwidth efficiency.
Data Source
AI summary
Examples include techniques associated with use of a memory tag with in-line or in-band error correction code (IBECC) memory to provide protection for data to be stored in an address space of a memory device. Examples include adding or including the memory tag with a single error correction double error detection (SECDED) code based on the data to provide IBECC for the data when stored to the first address space in the memory device.