Low-Latency iBUS Protocol for SoC Power Mitigation Alerts
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Solution Overview
Problem
Existing power management systems in system-on-chip (SoC) technologies face challenges with high latency in interrupt communication, leading to inefficient power mitigation and potential system instability due to prolonged communication latency in activating foldback mechanisms.
Innovation Solution
Implementing a low-latency interrupt bus interface (iBUS) with a flexible protocol that allows pre-assigned timeslots for priority interrupts, enabling shallow power mitigation by distributing alerts to processing cores without waiting for complete payload reception, thus reducing latency and maintaining system stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional interrupt protocol is used for power management communication, then system stability is maintained through complete payload reception, but interrupt latency increases significantly
Solution Approach 1:
The interrupt protocol payload is segmented into multiple timeslots, each assigned to specific peripheral devices. This allows the interrupt signal to be divided into discrete time units, enabling the SoC to process critical alert events immediately in their designated timeslots without waiting for the complete payload from all peripherals, thus reducing latency while maintaining systematic processing order.
Solution Approach 2:
Timeslots are pre-assigned to specific peripheral devices before interrupt transmission occurs. This preliminary assignment allows the SoC to prepare processing resources in advance and immediately process critical alerts when they occur, eliminating the need to wait for complete payload reception and significantly reducing interrupt latency while maintaining system stability through predetermined processing order.
2Productivity
If complete payload reception is required for interrupt processing, then data completeness is ensured, but power mitigation response time increases
Solution Approach 1:
The interrupt payload is segmented into multiple timeslots with each timeslot dedicated to specific peripheral devices. The SoC can process critical alert events from timeslots corresponding to power management peripherals immediately, without requiring complete payload reception from all peripherals, thus achieving fast power mitigation response while maintaining necessary alert information through the segmented timeslot structure.
Solution Approach 2:
Different timeslots have different processing priorities and requirements. Critical alert event timeslots for power management peripherals are processed with high priority and immediate response, while other peripheral timeslots can be processed subsequently. This local quality differentiation allows fast power mitigation response for critical events without compromising the completeness of overall payload processing.
3Loss of time
If pre-assigned timeslots are implemented for priority interrupts, then interrupt latency is reduced, but protocol complexity increases
Solution Approach 1:
Timeslots are pre-assigned to specific peripheral devices during system initialization or configuration phase. This preliminary assignment stores the mapping relationship between timeslots and peripherals in the SoC, enabling fast interrupt processing without complex runtime determination. The pre-assignment approach reduces interrupt response time while keeping the runtime protocol simple and manageable.
Solution Approach 2:
The timeslot assignment mechanism serves multiple functions: it provides latency reduction for priority interrupts, maintains systematic processing order for all peripherals, and enables flexible allocation of interrupt handling resources. This multi-functionality justifies the added protocol structure by delivering multiple benefits from a single mechanism.
Data Source
AI summary
Aspects of the disclosure relate to power management of a system-on-chip (SoC) and techniques of optimizing system performance and power management through power limits coordination via a low latency bus interface that provides a flexible protocol which enables high priority messages to facilitate power management. The protocol enables shallow power mitigation techniques to reduce the need of full mitigation of the apparatus.