Integrated Circuit Abstraction for Verification Efficiency
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Solution Overview
Problem
Current methods for integrated circuit design verification struggle with efficiently verifying functionality along data paths, especially when complex circuits are not built using standard intellectual property blocks, as they fail to effectively abstract specific state machines relevant to given properties.
Innovation Solution
A method that automatically abstracts portions of integrated circuits by selecting key signals, extracting corresponding sub-circuits, identifying intersection circuitry, and generating an abstraction model that includes paths from the intersection to the signals, allowing for focused verification of control logic within the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard abstraction methods are used for memory blocks and IP blocks, then verification efficiency is improved for standard blocks, but complex circuits without standard IP blocks cannot be effectively abstracted
Solution Approach 1:
The patent segments the complex circuit into multiple sub-circuits based on signal cones of influence. Each sub-circuit is extracted from a selected signal and includes all logic that drives that signal. This segmentation allows the verification system to handle complex non-standard circuits by breaking them into manageable abstracted portions, resolving the contradiction between verification efficiency and adaptability to non-standard designs.
Solution Approach 2:
The patent extracts specific sub-circuits from the larger circuit design by identifying cones of influence from selected signals. This extraction process creates simplified abstracted models that retain only the relevant logic for verification purposes. This taking out approach enables effective verification of complex circuits without requiring them to be built from standard IP blocks, thus improving both verification efficiency and adaptability.
2Reliability
If the entire circuit is used for verification, then complete coverage is achieved, but verification complexity and runtime increase significantly
Solution Approach 1:
The patent extracts only the necessary sub-circuits relevant to the verification property being tested, rather than using the entire circuit. By taking out only the cones of influence from selected signals that are pertinent to the verification goal, the system maintains verification coverage for the specific property while significantly reducing overall verification complexity and runtime.
Solution Approach 2:
The patent applies partial action by abstracting only the portions of the circuit that are necessary for verifying specific properties, rather than performing full-circuit verification. This partial abstraction approach achieves sufficient verification coverage for the given property while reducing complexity, demonstrating that complete verification of entire circuits is often excessive for targeted property verification.
3Measurement precision
If detailed circuit descriptions are used, then accurate verification is possible, but the number of logic components complicates the verification testing
Solution Approach 1:
The patent extracts sub-circuits that contain only the logic components necessary to verify the selected property, eliminating unnecessary logic components from the verification model. This extraction maintains verification accuracy by preserving the relevant circuit behavior while reducing the number of logic components that complicate testing, thus resolving the contradiction between precision and complexity.
Solution Approach 2:
The patent segments the detailed circuit description into smaller sub-circuit abstractions based on signal cones of influence. Each segmented sub-circuit contains only the logic components relevant to driving specific signals, which maintains verification accuracy for those signals while reducing the overall number of logic components that need to be tested, thereby resolving the contradiction between measurement precision and device complexity.
Data Source
AI summary
A system, such as a computer aided design (CAD) system, is configured to abstract at least a portion of an integrated circuit (IC) design provided thereto. The system selects two signals of the IC and determines the respective sub-circuits ending at each of the signals, excluding the other sub-circuit when two sub-circuits intersect. It then identifies an intersection of the two sub-circuits and therefore establishes an abstraction therefrom. The abstraction replaces the circuit for verification purposes of the IC design. The process can repeat as may be necessary or until no two signals have sub-circuits that intersect. The process described for two signals is equally applicable to a plurality of signals for which the intersection is defined as the intersection of all the sub-circuits defined by the plurality signals. The abstraction allows for effective verification of portions of ICs as may be necessary.