IC Alignment Marks for Precise Chip Mounting
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Solution Overview
Problem
The miniaturization of integrated circuits with complex structures leads to increased numbers and decreased sizes of bumps, making accurate alignment on substrates challenging, prone to shorts or misalignment during mounting.
Innovation Solution
Incorporating internal and external alignment marks, including p-type semiconductor areas and NMOS transistors, on the integrated circuit substrate to facilitate precise alignment using infrared cameras, with external alignment marks on the insulating layer and internal marks defined by p-type semiconductor absence or presence, ensuring accurate positioning during chip mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the size of the integrated circuit is miniaturized and the structure is complicated, then the integration density and functionality are improved, but the alignment accuracy during mounting deteriorates due to increased bump count and decreased bump size
Solution Approach 1:
Alignment marks are introduced as intermediary elements that facilitate the alignment process between the integrated circuit and substrate. These marks serve as reference points that enable accurate positioning despite the miniaturized scale and increased complexity of the circuit structure.
Solution Approach 2:
Alignment marks are pre-formed on the integrated circuit substrate during the semiconductor manufacturing process, before the mounting stage. This preliminary action ensures that alignment references are already in place when the circuit needs to be mounted, eliminating the need for post-manufacturing alignment adjustments.
2Quantity of substance
If the number of bumps increases and the size of bumps decreases, then the signal I/O capacity is improved, but the risk of short between bumps and misalignment increases
Solution Approach 1:
Alignment marks act as intermediary reference elements that enable precise positioning of the integrated circuit relative to the substrate. This precise positioning ensures that bumps are correctly aligned with their corresponding pads, preventing misalignment and short circuits despite the high density of bumps.
Solution Approach 2:
The patent replaces manual or粗放 alignment methods with an optical detection system that uses alignment marks. Infrared cameras or optical detection devices detect the alignment marks to automatically position the circuit with high precision, substituting mechanical alignment approaches that are insufficient for high-density bump structures.
3Manufacturing precision
If alignment marks are added to facilitate accurate positioning, then the mounting alignment accuracy is improved, but the device complexity and manufacturing steps increase
Solution Approach 1:
The alignment marks are merged with the existing semiconductor manufacturing processes. The p-type semiconductor regions that form the alignment marks are created using the same doping and processing steps already required for the circuit functionality, rather than adding separate dedicated alignment mark formation steps.
Solution Approach 2:
The p-type semiconductor regions serve multiple functions: they provide electrical functionality within the circuit and simultaneously serve as alignment marks for mounting positioning. This multi-functionality reduces the need for separate alignment mark structures and minimizes additional manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances alignment accuracy and registration by utilizing both external and internal alignment marks, improving the reliability and efficiency of the chip mounting process.
Implementation Method 1
it is necessary to accurately align the integrated circuit on the substrate... utilizing both external and internal alignment marks, including p-type semiconductor areas and NMOS transistors, on the integrated circuit substrate to facilitate precise alignment using infrared cameras
Data Source
AI summary
An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an internal alignment mark including a p-type semiconductor that is overlapped by a metallic external alignment mark arranged on the upper surface of the insulating layer. The p-type semiconductor internal alignment mark can be viewed by an infrared camera during a mounting process of the integrated circuit.