Integrated Circuit Analysis Using Open Deterministic Sequencing
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Solution Overview
Problem
Full-chip analyses of integrated circuits have become prohibitively time-consuming as technology advances and design size increases, necessitating a more efficient method for determining physical or electrical attributes.
Innovation Solution
An open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in the integrated circuit layout, with a measuring tool obtaining data to determine attribute values for each window, and a data analyzer computing an overall value as a weighted average, allowing for incremental and uniform point distribution and iterative refinement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-chip analysis is performed to ensure comprehensive coverage and accuracy of attribute determination, then measurement precision is improved, but analysis time increases prohibitively
Solution Approach 1:
The patent divides the full-chip analysis into multiple sample windows distributed across the integrated circuit layout. Instead of analyzing the entire chip at once, the analysis is segmented into manageable portions (sample windows) that can be processed independently and in parallel, significantly reducing overall analysis time while maintaining comprehensive coverage through strategic distribution of windows across the chip.
Solution Approach 2:
The patent performs analysis on a partial representation of the full chip by selecting a defined number of sample windows that are distributed across the layout. This partial action approach provides a statistically representative sample of the entire chip's attributes without requiring exhaustive full-chip analysis, thereby achieving acceptable precision with reduced time investment.
2Ease of manufacture
If sample windows are selected using random distribution, then ease of implementation is improved, but uniformity of point distribution across the integrated circuit deteriorates
Solution Approach 1:
The patent employs a feedback mechanism in the point selection process where each new point is selected based on its distance from previously selected points. The system continuously monitors the distribution and adjusts subsequent point selections to maximize minimum distances, ensuring uniform distribution. This feedback-driven approach maintains stability in point distribution while remaining computationally feasible.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing coordinates of points that maximize minimum distances before the actual analysis begins. This preliminary generation of uniformly distributed points eliminates the need for complex real-time calculations during analysis, maintaining ease of implementation while ensuring uniform distribution across the integrated circuit layout.
Data Source
AI summary
Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.