IC Array Power Stacking Layout to Cut I2R Losses
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Solution Overview
Problem
Integrated circuits (ICs) operating at low power supply voltages face high current consumption and significant I2R power losses due to high current requirements, leading to inefficient voltage regulation and increased power dissipation, especially when multiple ICs are aggregated in systems.
Innovation Solution
The proposed solution involves an array of devices with staggered voltage distribution, where each device has a Vdd terminal with a higher potential than the Vss terminal, and the Vss terminals of subsequent devices in a column are connected in series, creating a staggered voltage drop across the array to reduce current requirements and minimize I2R losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low power supply voltage (200mV-500mV) is used to lower dynamic power dissipation, then power consumption is reduced, but current consumption increases significantly leading to high I2R power losses
Solution Approach 1:
The system segments the array of ICs into multiple columns (M columns) and distributes the power supply voltage across these columns using a voltage distribution network. Each column receives a portion of the total voltage, and the Vss terminals are connected in series to create staggered voltage drops. This segmentation allows the system to operate at low voltage per IC while reducing the aggregate current through the power distribution network, thereby minimizing I2R losses.
Solution Approach 2:
The patent introduces a column-based dimensional organization (M columns × N ICs per column) to the power distribution architecture. By adding the column dimension and implementing series connections of Vss terminals across columns, the system creates a two-dimensional voltage distribution pattern. This dimensional change enables staggered voltage drops that reduce current aggregation and minimize I2R power losses in the horizontal direction across the array.
2Productivity
If multiple ICs are aggregated in a system to meet high-performance compute demands, then processing capability is improved, but aggregate current increases leading to large IR drops and I2R power losses
Solution Approach 1:
The system segments the aggregated ICs into M columns with series-connected Vss terminals, creating M separate current paths. This segmentation distributes the aggregate current across multiple parallel paths, reducing the current through each individual power distribution path and thereby reducing I2R losses while maintaining the total processing capability of all ICs.
Solution Approach 2:
The patent implements local quality by providing different voltage levels to different columns through the staggered voltage distribution. Each column experiences a different voltage drop pattern, and the Vss terminal connections create localized voltage adjustments that optimize power delivery to each IC based on its specific position and requirements, reducing overall I2R losses.
3Loss of energy
If series power supply stacking is used to lower current requirement, then current through regulator is reduced, but additional voltages or power saving techniques cannot be provided
Solution Approach 1:
The system segments the voltage distribution into M columns with series-connected Vss terminals, creating a modular architecture that provides both current reduction and voltage flexibility. Each column can be independently configured with different voltage drops, allowing the system to provide multiple voltage levels while maintaining reduced current requirements through the regulator.
Solution Approach 2:
The patent implements multi-functionality by creating a voltage distribution network that simultaneously achieves current reduction (through series stacking) and provides additional voltage levels (through staggered voltage drops across columns). The same architectural structure serves both to reduce regulator current and to provide flexible voltage distribution for different power saving techniques and voltage requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power losses and improves efficiency by distributing voltage in a way that balances current consumption across multiple ICs, thereby minimizing the overall power dissipation in the system.
Implementation Method 1
the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i-1,j)
Implementation Method 2
creating a staggered voltage drop across the array to reduce current requirements and minimize I2R losses
Data Source
AI summary
Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i−1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M−1, wherein a sum of all Xj voltages for j=1:(M−1) is greater than 0.25*VDD.