Backside Power Contact Layout for Dense IC Power Distribution
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Solution Overview
Problem
Existing integrated circuit device fabrication methods face challenges in increasing integration density while simplifying the middle-of-line (MOL) and back-end-of-line (BEOL) portions, particularly in forming effective backside power distribution networks (BSPDN) without increasing complexity.
Innovation Solution
The integration of a power contact formed by replacing a placeholder in the substrate during the front-end-of-line (FEOL) portion, which allows for the formation of a BSPDN structure that simplifies the MOL and BEOL portions by electrically connecting the source/drain region to a power rail, with the power contact extending through the substrate and interlayer, enabling efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If elements are formed in a substrate or on a backside of the substrate to simplify MOL and BEOL portions, then device fabrication complexity is reduced, but integration density increases only moderately
Solution Approach 1:
The invention moves power distribution elements from the traditional planar front-side layout to the vertical dimension by forming power contacts through the substrate thickness and positioning power rails on the backside. This three-dimensional arrangement allows power distribution to occur in the depth direction, freeing up horizontal space for additional functional elements and thereby increasing integration density while maintaining simplified fabrication processes.
Solution Approach 2:
The invention introduces sacrificial elements as intermediary structures that are formed during FEOL,然后通过选择性去除这些牺牲元素来创建power contact孔。这种中介方法使得power contact能够在不增加MOL/BEOL复杂性的情况下精确形成，同时为后续的power rail连接提供准确的定位和尺寸控制。
2Reliability
If a BSPDN structure is formed to connect power rails to source/drain regions, then power distribution efficiency is improved, but fabrication complexity increases
Solution Approach 1:
The invention performs preliminary actions by forming sacrificial elements during the FEOL portion before the main transistor fabrication. These sacrificial elements predefine the locations and dimensions of future power contacts, ensuring precise alignment with source/drain regions. This preliminary structuring eliminates the need for complex alignment procedures during later power distribution network formation, thereby achieving efficient power delivery without increasing overall fabrication complexity.
Solution Approach 2:
Instead of forming power contacts by direct patterning and etching through the substrate, the invention inverts the approach by first forming sacrificial elements that protrude from the substrate surface, then selectively removing portions of the substrate around them. This inverted methodology simplifies the formation of precise power contact holes and their alignment with underlying source/drain regions, reducing fabrication complexity while maintaining reliable electrical connections.
3Reliability
If power contact extends through substrate and interlayer to enable BSPDN, then power distribution network effectiveness is improved, but manufacturing steps increase
Solution Approach 1:
The invention merges multiple functions into the power contact structure: it serves as both the electrical connection element and the structural template for defining the power distribution network layout. By combining the roles of alignment reference, electrical conductor, and structural support in a single integrated element, the design achieves effective BSPDN formation without proportionally increasing manufacturing steps. The power contact simultaneously fulfills multiple requirements that would otherwise need separate processing steps.
Solution Approach 2:
The sacrificial elements and power contacts are designed to self-align with source/drain regions through their geometric relationships and formation sequences. The power contact structure inherently defines its own positioning through the sacrificial element framework, eliminating the need for additional alignment procedures or complex lithographic steps. This self-aligning capability reduces the number of manufacturing steps required while ensuring effective electrical connections for the BSPDN.
Data Source
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AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including a channel region (22_1) and a source/drain region (26_2) contacting the channel region (22_1), a power rail (72) that is configured be electrically connected to a power source and is spaced apart from the source/drain region (26_2) in a first direction (Z), and a power contact (62) that is between the source/drain region (26_2) and the power rail (72) and contacts both the source/drain region (26_2) and the power rail (72). The channel region (22_1) may overlap the power contact (62) in the first direction (Z).