IC Backside Thinning With Si-Selective Polishing at the STI Level
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing backside thinning processes for integrated circuits (ICs) face challenges in achieving accurate and reliable thinning, especially at the shallow trench isolation (STI) level, due to the need for high selectivity in Si removal and the difficulty in achieving a reliable endpoint without damaging functional components.
Innovation Solution
A method involving the use of a polishing pad and a slurry configured for Si-selective removal under mechanical shear force, allowing for controlled thinning of the IC's backside to a thickness of 1 µm or less while maintaining the integrity of the STI level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional mechanical polishing is used to thin the IC backside, then material removal speed is improved, but selectivity between Si substrate and Si-based insulator deteriorates
Solution Approach 1:
The invention changes the chemical composition parameters of the polishing slurry by incorporating specific chemicals (such as potassium hydroxide, tetramethylammonium hydroxide, or ammonium hydroxide) in controlled concentrations (0.1-10 wt%). This chemical modification enables selective removal of Si substrate while preserving Si-based insulators like silicon dioxide and silicon nitride, achieving both high removal speed and high selectivity simultaneously
Solution Approach 2:
The invention creates a composite polishing slurry system that combines abrasive particles (for mechanical removal) with chemically active components (alkali metals, organic compounds). This composite formulation synergistically combines mechanical polishing efficiency with chemical selectivity, allowing the slurry to differentiate between Si substrate and Si-based insulators while maintaining high material removal rates
2Productivity
If aggressive thinning is applied to achieve 1 μm or less thickness, then thinning speed is improved, but risk of damaging functional components increases
Solution Approach 1:
The invention implements feedback control through continuous monitoring of thinning progress using techniques such as optical interference, reflectometry, or ellipsometry. The system measures the backside thickness in real-time and automatically adjusts polishing parameters (pressure, speed, slurry flow) to maintain the thickness within the target range (1 μm or less), preventing over-thinning and damage to functional components
Solution Approach 2:
The invention applies a protective cushioning layer or conditioning treatment to the IC backside before aggressive thinning begins. This preliminary protection layer, or pre-conditioning of the polishing interface, cushions against mechanical shocks and chemical attacks during the aggressive thinning process, preventing damage to underlying functional components while still allowing rapid material removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables reliable and accurate thinning of ICs down to the STI level, allowing for efficient probing and analysis using visible light or electron beams, while ensuring the functionality of the IC components remains intact.
Implementation Method 1
applying a slurry onto the polishing pad and/or the backside of the IC, the slurry being configured to provide an at least Si-selective removal upon exertion of a mechanical shear force
Implementation Method 2
thinning the IC to a thickness of the Si-containing substrate of 1 μm or less by exerting a mechanical shear force to the IC's backside
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
The present invention relates to a method for backside thinning of an integrated circuit, herein referred to as IC. The method comprises the steps of: - providing the IC, wherein the IC comprises a Si-containing substrate forming the backside of the IC, a Si-based insulator-containing shallow trench isolation, herein referred to as STI, arranged on the Si-containing substrate and one or more functional IC components arranged within the STI and/or on the STI opposite the Si-containing substrate, - providing a polishing pad, - applying a slurry onto the polishing pad and/or the backside of the IC, the slurry being configured to provide an at least Si-selective removal upon exertion of a mechanical shear force, - bringing the backside of the IC and the polishing pad into contact with each other, and - thinning the IC to a thickness of the Si-containing substrate of 1 µm or less by exerting a mechanical shear force to the IC's backside while maintaining the contact between the IC and the polishing pad up.