Integrated Circuit Backside Wiring for Lower Source Resistance

The patent introduces a backside wiring layer beneath the substrate, adding a new dimensional space for routing power and signal lines. This allows critical current paths to be formed using vias that penetrate or traverse the substrate, effectively moving wiring from a planar constraint to a three-dimensional configuration. The backside wiring layer enables power delivery without occupying additional planar area, thus maintaining high integration density while providing alternative current paths that reduce parasitic resistance and capacitance effects.

By routing power supply lines through the backside wiring layer and using vertical vias to connect to frontside circuitry, the patent creates shorter and more direct current paths. This three-dimensional wiring approach reduces the length of power delivery networks, thereby minimizing parasitic resistance and inductance. The reduced parasitic effects ensure that even at lower operating voltages, sufficient current can be delivered to maintain proper circuit operation, enabling effective power management without sacrificing performance.

The patent divides the wiring function into two separate layers: frontside wiring for signal routing and backside wiring for power delivery and interconnect. This segmentation allows each layer to be optimized independently for its specific function. The backside wiring layer handles high-current power paths and critical signal interconnects, while the frontside layer focuses on signal integrity and logic routing. This functional separation simplifies the overall routing complexity by preventing wire congestion and design rule conflicts that would arise from attempting to route all signals and power in a single planar layer.

The patent utilizes vertical vias that traverse the substrate to connect the backside wiring layer to frontside transistor sources. These vertical interconnects provide low-resistance current paths that are independent of planar wire dimensions. By delivering power through the substrate thickness rather than through narrow planar wires, the patent effectively reduces source resistance without consuming additional lateral area. This three-dimensional power delivery approach maintains compact circuit footprints while ensuring adequate current supply to transistor sources.