Integrated Circuit Thermal Reliability via BIST Timing Constraints
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Solution Overview
Problem
Integrated circuit devices face unpredictable behavior and reduced functionality when operating temperatures exceed their guaranteed maximum, due to varying timing characteristics, which existing designs fail to address effectively.
Innovation Solution
Incorporating over-constrained timing requirements in primary circuitry and normal timing constraints in secondary circuitry, along with built-in self-test (BIST) circuitry, to ensure continued operation above the maximum operating temperature by powering down selective circuitry and replicating critical functional blocks with stringent timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If integrated circuit devices operate above the guaranteed maximum temperature, then the device can handle higher thermal loads, but unpredictable behavior and reduced functionality occur due to timing characteristic variations
Solution Approach 1:
The patent implements dynamic timing constraints that adapt to temperature conditions. Over-constrained timing requirements are applied to critical functional blocks to maintain reliability at elevated temperatures, while normal timing constraints are used for non-critical blocks. This dynamic allocation of timing margins allows the system to operate reliably across a wider temperature range.
Solution Approach 2:
The integrated circuit is divided into primary circuitry with over-constrained timing requirements and secondary circuitry with normal timing constraints. This segmentation allows different parts of the system to have different reliability margins, enabling the critical functions to maintain predictability at high temperatures while non-critical functions can be powered down or operate with reduced margins.
2Reliability
If over-constrained timing requirements are applied to primary circuitry, then reliability above maximum temperature is improved, but device complexity increases
Solution Approach 1:
Different timing constraint strategies are applied to different parts of the circuit based on their criticality. Primary circuitry that must operate reliably at high temperatures receives over-constrained timing requirements, while secondary circuitry uses normal timing constraints. This localized application of quality measures maintains reliability where needed without unnecessarily complicating the entire device.
Solution Approach 2:
The patent uses built-in self-test (BIST) circuitry that replicates the functionality of primary circuit blocks to verify their operation. This copying mechanism allows the system to detect and respond to failures in real-time, maintaining reliability without requiring complete redesign of the primary circuitry with excessive margins.
3Measurement precision
If built-in self-test circuitry is implemented, then detection of timing failures is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The built-in self-test (BIST) circuitry enables the integrated circuit to autonomously monitor and verify its own operation. The BIST logic periodically tests the primary circuitry for timing failures and can trigger corrective actions such as powering down affected blocks or alerting external systems. This self-service capability provides continuous verification without requiring external test equipment, improving measurement precision while keeping the added complexity contained within the device.
Data Source
AI summary
Devices, systems and methods of this disclosure can provide integrated circuit devices operating above their specified operating temperate. The integrated circuit device can include functional blocks with power down circuitry and functional test blocks with built in self-test capabilities (BIST). The functional blocks can be implemented with timing constraint values to provide a timing margin for the device above a specified operation temperature. The functional test blocks can be implemented with timing constraint values that result in BIST failure when the device is operated above the specified operation temperature. As the temperature of the device rises above the operating temperature the functional test blocks can fail BIST prior to loss of functionality of the functional blocks. Upon BIST failure of the functional test blocks, circuitry in the functional blocks can be powered down to facilitate continued operation of the device with reduced functionality.