Intrinsic Capacitance Estimation for IC Blocks
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Solution Overview
Problem
The design gap between silicon manufacturing advances and designers' productivity leads to underutilized silicon in integrated circuits, exacerbated by 'deep submicron' problems such as non-convergent timing and complex electrical effects, making it challenging to estimate peak current demands and intrinsic capacitance accurately for high-performance memory designs.
Innovation Solution
A method and system for approximating intrinsic capacitance of an IC block by estimating N-well, metal grid, and non-switching circuitry capacitances, allowing for accurate peak current estimation and external decoupling capacitance design, using a computer-implemented system and program product that models these components efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional EDA tools and design methodologies are used, then design productivity is maintained at current levels, but silicon utilization decreases due to the design gap between manufacturing advances and designers' productivity
Solution Approach 1:
The patent changes the parameter of capacitance estimation from traditional complex extraction methods to a simplified model-based approach. By using analytical models to estimate N-well, metal grid, and non-switching circuitry capacitances, the system achieves faster computation while maintaining adequate accuracy for decoupling capacitor design, thereby improving designers' productivity without sacrificing essential design quality.
Solution Approach 2:
The patent segments the total intrinsic capacitance into three distinct components: N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance. Each component is estimated separately using specialized models, allowing for more efficient computation compared to traditional full-extraction methods, thus addressing the productivity-silicon utilization contradiction.
2Measurement precision
If accurate peak current estimation is performed using traditional methods, then measurement precision is improved, but computational complexity and time increase due to complex electrical effects in deep submicron processes
Solution Approach 1:
The patent changes the approach from full electromagnetic extraction to analytical capacitance modeling. By using closed-form equations to estimate the three capacitance components (N-well, metal grid, non-switching circuitry), the system reduces computational complexity significantly while maintaining sufficient accuracy for peak current and decoupling capacitor design in deep submicron processes.
Solution Approach 2:
The patent employs simplified analytical models that are computationally inexpensive and fast to evaluate, replacing expensive and time-consuming traditional extraction tools. These lightweight models provide adequate accuracy for design decisions without requiring complex computational resources, thus reducing device complexity while maintaining measurement precision.
3Reliability
If comprehensive capacitance extraction is performed to account for all electrical effects, then reliability is improved, but design time increases due to complicated timing and extraction requirements
Solution Approach 1:
The patent changes the methodology from comprehensive full-waveform extraction to targeted analytical modeling of the three dominant capacitance components. This approach maintains reliability for decoupling capacitor design by capturing the essential electrical effects (N-well, metal grid, and non-switching circuitry contributions) while reducing design time through faster computation of closed-form equations.
Solution Approach 2:
The patent extracts and focuses only on the three most significant capacitance components that dominate the intrinsic capacitance behavior in typical IC blocks. By taking out and modeling only these critical elements (N-well, metal grid, non-switching circuitry) rather than performing exhaustive extraction of all parasitic elements, the system achieves adequate reliability with reduced design time.
Data Source
AI summary
A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compliable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.