IC Design Blockage Layers for Parasitic Capacitance Reduction
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Solution Overview
Problem
The reduction in width between metal layers of integrated circuits leads to increased parasitic capacitance due to dummy patterns, resulting in performance loss during the CMP process, which existing technologies have not adequately addressed.
Innovation Solution
An integrated circuit design system using a computing system that generates blockage layers at specific levels surrounding metal layers to prevent parasitic capacitance by optimizing the placement and spacing of metal and dummy patterns, thereby improving reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy patterns are added between metal layers to prevent dishing during CMP process, then dishing prevention is improved, but parasitic capacitance increases
Solution Approach 1:
The invention divides the blockage layer into multiple segments at different levels (first blockage layer at the same level as the metal layer, second blockage layer at a higher level, and third blockage layer at a lower level). This segmentation allows each blockage layer segment to serve specific functions: the first segment prevents dishing at the metal layer level, while the second and third segments prevent parasitic capacitance formation by blocking electric field lines, thereby resolving the contradiction between dishing prevention and parasitic capacitance reduction
Solution Approach 2:
The invention extends the solution from a single-plane approach to a multi-dimensional approach by creating blockage layers at multiple vertical levels (different z-coordinates). The first blockage layer operates at the metal layer level, the second blockage layer operates at a higher level to block upward electric field lines, and the third blockage layer operates at a lower level to block downward electric field lines. This dimensional extension allows simultaneous achievement of dishing prevention and parasitic capacitance reduction
2Area of stationary object
If width between metal layers is reduced to improve degree of integration, then chip size is reduced, but parasitic capacitance increases
Solution Approach 1:
The invention introduces blockage layers as intermediary structures between metal layers. These blockage layers act as mediators that block electric field lines and prevent parasitic capacitance formation between adjacent metal layers. By placing blockage layers at strategic positions (same level, higher level, and lower level), the invention enables closer metal layer spacing for higher integration while maintaining low parasitic capacitance through the intermediary blocking action
3Object-generated harmful factors
If blockage layers are generated at multiple levels surrounding metal layers, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The invention applies blockage layers with local quality differentiation: the first blockage layer at the same level as the metal layer has the quality of preventing dishing through mechanical support during CMP, while the second blockage layer at a higher level and the third blockage layer at a lower level have the quality of blocking electric field lines to prevent parasitic capacitance. Each blockage layer segment is strategically positioned and sized to address specific local requirements, achieving effective parasitic capacitance reduction while maintaining reasonable structural complexity through targeted rather than universal application
Data Source
AI summary
An integrated circuit design system using a computing system comprises a processor, and memory configured to store an instruction, which allows the processor to perform a method of designing an integrated circuit, the integrated circuit includes a substrate, a front end of line (FEOL) in at least a portion of the substrate and on the substrate, and a back end of line (BEOL) formed on the FEOL, and the method of designing the integrated circuit includes selecting a first metal layer included in the BEOL and disposed at a first level from the substrate, generating a first blockage layer disposed at the first level, surrounding the first metal layer, generating at least one first upper blockage layer disposed at a level higher than the first level from the substrate, and generating at least one first lower blockage layer disposed at a level lower than the first level from the substrate.