IC Substrate Bonding Structure for Overlay Precision in BSPDN
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The downscaling of IC devices poses challenges in maintaining overlay precision and minimizing bending distortion and overlay errors as semiconductor substrates become thinner and pattern sizes are reduced, affecting critical dimension uniformity and reliability.
Innovation Solution
A novel IC device structure is introduced, featuring a first and second semiconductor substrate with a back-side power delivery network (BSPDN) that includes a wiring structure on the backside, utilizing a second BEOL structure bonded to a second semiconductor substrate with local trench regions and air gaps to enhance overlay precision and bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor substrate is made thinner to achieve higher integration, then device integration density is improved, but bending distortion and overlay errors increase
Solution Approach 1:
The substrate structure is segmented into multiple functional layers including front-side BEOL, back-side BEOL, and intermediate bonding layers. The back-side BEOL is further segmented into bonding areas and local trench regions, distributing stress and preventing substrate bending distortion while maintaining thin substrate thickness for high integration
Solution Approach 2:
Different regions of the substrate are assigned different properties: bonding areas have high adhesion strength for mechanical support, while local trench regions provide stress relief. This local differentiation allows the substrate to maintain both thinness and dimensional stability, preventing overlay errors during manufacturing
2Area of moving object
If pattern sizes are reduced to achieve higher integration, then device density is improved, but overlay errors and critical dimension uniformity deteriorate
Solution Approach 1:
The back-side BEOL structure with local trenches and bonding areas is prepared in advance before front-side pattern formation. This preliminary structural preparation establishes a stable mechanical foundation that prevents substrate bending and maintains flatness, ensuring consistent overlay precision and critical dimension uniformity even when patterns are scaled down to smaller sizes
Solution Approach 2:
The solution moves from two-dimensional pattern scaling to three-dimensional structural engineering by incorporating vertical layering with back-side BEOL and local trenches. This dimensional transition provides mechanical stability in the vertical direction, compensating for the reduced dimensional tolerance caused by smaller pattern sizes and maintaining manufacturing precision
3Strength
If local trench regions are formed in the second semiconductor substrate, then bonding strength and overlay precision are improved, but device structure complexity increases
Solution Approach 1:
The second semiconductor substrate is segmented into bonding areas and local trench regions, creating a modular structure that enhances bonding strength through localized stress distribution. This segmentation approach achieves improved mechanical properties without requiring complete structural redesign, thereby limiting the increase in overall device complexity
Data Source
AI summary
An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.


