IC Connection Buffer with Level Shifting for Mixed-Voltage Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing connection devices for integrated circuits are limited in connecting external components with operating voltages higher than the supply voltage, leading to potential noise and overconsumption due to increased conductivity in PMOS transistors, which is not compatible with the trend of lowering circuit supply voltages.
Innovation Solution
Incorporating a voltage comparator and voltage level shifters to generate control signals for active transistors, allowing the connection of external components with operating voltages different from the supply voltage, and using a control circuit to manage the conductivity of the buffer, ensuring non-conductivity even when the external component's voltage is higher.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the supply voltage of the integrated circuit is lowered to meet current trends, then energy consumption is reduced, but the ability to connect external components with higher operating voltages is lost
Solution Approach 1:
The patent introduces a voltage level shifter as an intermediary component between the external component and the integrated circuit buffer. This level shifter translates the higher voltage from the external component to the lower supply voltage of the IC, allowing connection without requiring the IC to operate at higher voltages. The buffer remains protected while the external component can operate at its required voltage level.
2Adaptability or versatility
If the gate voltage of the PMOS transistor is increased to allow connection of higher voltage external components, then voltage compatibility is improved, but noise and current injection problems occur
Solution Approach 1:
The voltage level shifter acts as a mediator that prevents direct high-voltage connection to the PMOS gate. It transforms the external component's higher voltage into the appropriate lower voltage level for the IC's supply voltage, thereby maintaining voltage compatibility without exposing the PMOS transistor to harmful high voltages that cause noise and current injection.
Solution Approach 2:
The patent dynamically adjusts the voltage level parameter at the gate of the PMOS transistor through the voltage level shifter. Instead of fixing the gate voltage to match external components, the system changes the voltage parameter to always remain at the safe IC supply voltage level, regardless of the external component's operating voltage.
3Device complexity
If a simple inverter buffer is used for connection, then device complexity is reduced, but protection against voltage mismatches is insufficient
Solution Approach 1:
The voltage level shifter is inserted as an intermediary between the external component and the simple inverter buffer. This adds minimal complexity to the overall structure while providing essential protection against voltage mismatches. The buffer remains simple, but the level shifter ensures reliable operation by preventing voltage compatibility issues.
Data Source
Figure 1~2
Figure 3
AI summary
The device (1) has active transistors (N1, P1) e.g. N and P-type metal-oxide-semiconductor active transistors, mounted in series between a supply voltage (V-DD) and a ground (V-SS). A switching unit (3) modifies an amplitude level of voltage signals (V-esd) applied to gates of active transistors without exceeding a highest voltage of the supply voltage or an internal regulated voltage (V-REG), so as to adapt a voltage domain of an integrated circuit to an external component connected to an external contact pad (2).