High Power IC Bump Pads Shunting Current to Workpiece
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Solution Overview
Problem
High power integrated circuit (IC) devices face significant heating issues due to high current densities, leading to performance degradation and parasitic effects, which hinder miniaturization and efficiency, especially as circuit density increases, and conventional cooling methods often result in increased package size with minor heating reduction.
Innovation Solution
Shunting high power signals through a workpiece instead of metallization layers within the IC, by connecting coacting current conducting nodes like source and drain nodes of MOS transistors to bump pads on the IC surface, allowing current combination in the workpiece, thereby reducing current density and parasitic effects, and enabling closer placement of control ICs or integrating control circuits within the same IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high current densities are used in high power ICs to increase power output, then power output increases, but heating of the MCM package increases causing performance degradation
Solution Approach 1:
The patent extracts the high current carrying function from the IC metallization layers and relocates it to external MCM package traces. The IC only retains low current control circuits, while high power signals are routed through the package substrate, removing the heat-generating high current paths from the IC itself.
Solution Approach 2:
The MCM package substrate acts as an intermediary that handles high current signals between the IC and the external circuit. The package traces serve as mediator pathways that can carry high currents without affecting the IC's internal thermal environment, as the heat is dissipated in the package rather than the IC.
2Temperature
If ICs are spaced apart on the MCM package surface to improve thermal characteristics, then heat dissipation improves, but the MCM package size increases
Solution Approach 1:
The patent extracts the thermal management burden from the IC placement configuration and relocates it to the package substrate design. By moving high current paths to the package, heat generation is separated from the ICs, allowing compact IC placement without compromising thermal performance.
3Speed
If high power signals are routed through metallization layers within the IC, then signal transmission is achieved, but parasitic effects and heating increase
Solution Approach 1:
The patent extracts high power signal routing from the IC's internal metallization layers and relocates it to the MCM package substrate traces. This separation removes the source of parasitic effects and resistive heating from the IC's sensitive control circuitry while maintaining signal transmission functionality.
4Productivity
If the number of ICs in the MCM package increases to achieve higher circuit density, then circuit density increases, but heating effects are exacerbated
Solution Approach 1:
The patent extracts the thermal management challenge from the IC density configuration and relocates it to the package-level current distribution architecture. By routing all high current paths through the package substrate rather than individual ICs, multiple ICs can be densely packed without compounding thermal issues, as each IC operates at lower current levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces heating and parasitic effects within the IC, allowing for more aggressive miniaturization, increased application flexibility, and reduced costs by combining high power signals outside the IC, thus improving overall efficiency and performance.
Implementation Method 1
connecting coacting current conducting nodes like source and drain nodes of MOS transistors to bump pads on the IC surface
Implementation Method 2
The workpiece can include the conducting bands on a workpiece surface, where the conducting bands are configured for contacting the bump pads of the IC associated with the high power nodes. Accordingly, the currents at the coacting current conducting nodes of the high power devices in the IC are combined in the workpiece
Data Source
AI summary
An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.