Integrated Circuit Burn-In and Automated Test Merging
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Solution Overview
Problem
The testing of semiconductor devices is a time-consuming process, particularly due to the need for separate burn-in and automated tests, which can be prolonged when failures are detected, and existing methods require costly equipment like burn-in boards or ovens.
Innovation Solution
A method and system for simultaneously performing burn-in and automated tests on integrated circuits, utilizing a carrier wafer with heater chips to apply thermal stress, allowing for a unified testing process without external burn-in boards or ovens, thereby reducing testing time and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate burn-in and automated tests are performed sequentially, then testing completeness is improved, but testing time increases significantly
Solution Approach 1:
The patent combines separate burn-in testing and automated functional testing into a single unified test process. The integrated circuit is subjected to elevated temperature conditions while simultaneously performing automated functional tests, eliminating the need for sequential testing and significantly reducing total testing time while maintaining both reliability assessments.
Solution Approach 2:
The testing system is designed to perform multiple testing functions simultaneously - both burn-in stress testing and automated functional testing are conducted in the same test environment and time frame. This multi-functional approach allows the system to assess both reliability under stress and functional performance without requiring separate dedicated test equipment or time slots.
2Reliability
If traditional burn-in boards or ovens are used, then burn-in testing capability is improved, but equipment cost increases
Solution Approach 1:
The testing system uses a single unified test platform that performs both automated functional testing and burn-in stress testing without requiring separate dedicated equipment. By integrating temperature control capabilities into the existing automated test system, the patent eliminates the need for expensive separate burn-in boards or ovens while maintaining full burn-in testing capability.
Solution Approach 2:
The patent merges the functions of automated test equipment and burn-in stress equipment into a single integrated system. The test chamber or test environment is designed to provide both functional test signals and controlled elevated temperature conditions, eliminating the need for parallel equipment investments and reducing overall system complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly shortens the testing time by enabling simultaneous burn-in and automated testing, and eliminates the need for expensive equipment, thereby enhancing efficiency and reducing the time required to detect failures in integrated circuits.
Implementation Method 1
utilizing a carrier wafer with heater chips to apply thermal stress
Data Source
AI summary
A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.