Hybrid-Bonded IC-Capacitor Assembly for Low ESL/ESR Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrating capacitors and integrated circuits in a circuit assembly while avoiding wire bonding or solder mounting, and achieving high performance computing with low ESL and ESR, is challenging due to the complexity of electronic systems and the need for high capacitance values.
Innovation Solution
A circuit assembly is designed with an IC die and a capacitor die stacked together using hybrid bonding layers, allowing electrical coupling without wire bonding or solder mounting, and featuring a stack of capacitor dies to provide high capacitance and low ESL/ESR, enabling efficient signal transmission and power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding or solder mounting is used to integrate capacitors and ICs, then electrical connection is achieved, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent merges the capacitor die and IC die into a single integrated package with shared substrate, eliminating the need for separate wire bonding or solder mounting processes. The hybrid bonding layer directly couples the capacitor die to the IC die, combining what were previously separate assembly steps into an integrated manufacturing process.
Solution Approach 2:
The patent introduces a hybrid bonding layer as an intermediary between the capacitor die and IC die. This bonding layer serves as a mediator that provides both mechanical support and electrical connection, replacing the need for traditional wire bonding or solder mounting intermediaries.
2Reliability
If traditional capacitor integration methods are used, then electrical connection is established, but ESL and ESR values remain high
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. By stacking capacitor dies vertically and utilizing multiple bonding layers, the design achieves lower ESL and ESR values by reducing current path length and improving electrical coupling efficiency in the vertical dimension.
Solution Approach 2:
The patent employs a composite structure combining multiple dielectric materials and conductive bonding layers. The hybrid bonding layer integrates different material properties to simultaneously achieve low ESL, low ESR, and high capacitance density, creating a composite solution that addresses multiple performance requirements.
3Reliability
If high capacitance values are achieved through multiple capacitors, then power supply stability improves, but device area and integration difficulty increase
Solution Approach 1:
The patent achieves high total capacitance by stacking capacitor dies in the vertical dimension rather than placing them side-by-side in the planar dimension. This three-dimensional arrangement allows multiple capacitors to share the same footprint area, dramatically reducing the overall device area while maintaining high capacitance values for power supply stability.
4Quantity of substance
If stacked capacitor structure is implemented, then capacitance density increases, but manufacturing precision requirements increase
Solution Approach 1:
The hybrid bonding layer serves multiple functions simultaneously: mechanical support, electrical connection, and alignment reference. By making the bonding layer multi-functional, the design reduces the need for separate alignment features and simplifies the manufacturing process, thereby reducing precision requirements despite the stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high performance computing by providing numerous IPD capacitors as decoupling capacitors or flying capacitors, achieving high capacitance values and low ESL/ESR, thus enhancing power supply stability and efficiency without the need for wire bonding or solder mounting.
Implementation Method 1
The IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer
Data Source
AI summary
A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.