IC Cell Structure With Backside Power Delivery and Deep Via Boundaries
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, necessitating new methodologies or technologies to optimize performance and area efficiency.
Innovation Solution
The implementation of a 4 M0 signal routing track architecture with backside power delivery through deep via boundaries, allowing for reduced cell height, lower power network resistance, and improved performance by eliminating front-side power delivery networks, enabling tighter pitch control and increased routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing compatibility and cost are maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node and below
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming gate lines with first pitch, then forming trench contacts with second pitch that is a multiple of the first pitch. This segmentation allows each stage to be optimized independently, achieving precise feature sizes at 10nm node while using conventional fabrication techniques.
Solution Approach 2:
The patent introduces pitch as a dimensional parameter to resolve the contradiction. By establishing that the second pitch (trench contacts) is a multiple of the first pitch (gate lines), the patent creates a scalable relationship that maintains manufacturing precision across different technology nodes without requiring entirely new fabrication processes.
2Area of moving object
If feature size is scaled down to increase device density, then area efficiency improves, but fabrication process variability increases
Solution Approach 1:
The patent addresses fabrication variability by introducing a pitch relationship in the vertical dimension (from gate lines to trench contacts). By making the second pitch a multiple of the first pitch, the design creates inherent scaling relationships that maintain reliability even as feature sizes decrease to increase device density.
3Use of energy by moving object
If front-side power delivery networks are used, then power distribution is achieved, but cell height increases and routing efficiency decreases
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the backside of the substrate through through-silicon vias rather than through the front-side interconnect network. This inversion eliminates the need for dedicated power delivery networks on the front side, reducing cell height and simplifying the interconnect structure while maintaining power delivery capability.
4Adaptability or versatility
If more signal routing tracks are implemented, then routing capabilities improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent manages manufacturing precision requirements by establishing a pitch relationship where the second pitch (trench contacts) is a multiple of the first pitch (gate lines). This allows for increased routing flexibility through additional signal tracks while maintaining manufacturability through the scalable pitch relationship that works within conventional fabrication capabilities.
Data Source
AI summary
Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.