IC Cell IO Track Alignment for Direct M0 Routing
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Solution Overview
Problem
Current integrated circuit (IC) design and manufacturing processes face challenges in efficiently routing and placing cells within IC layouts due to constraints on spacing and connectivity, leading to increased resource consumption and chip area usage.
Innovation Solution
The implementation of cells with restricted IO patterns to specific tracks in a metal layer, providing multiple versions of cells with corresponding IO patterns in different tracks, and using cells with multiple IO patterns and floating conductive patterns that can be configured as IO patterns in different tracks, allows for simplified routing and reduced resource usage by aligning IO patterns for direct connection in the same metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cells are placed with standard spacing and routing rules, then connectivity between cells is achieved, but routing resources and chip area are increased
Solution Approach 1:
The patent applies dimensionality change by utilizing the vertical stacking of metal layers (from 2D planar routing to 3D spatial routing). IO patterns are distributed across multiple metal layers (M0, M1, M2, etc.), allowing connections to be made in the vertical dimension. This reduces the need for extensive lateral routing in the chip plane, thereby reducing chip area while maintaining connectivity.
Solution Approach 2:
The patent segments the IO patterns into different metal layers based on their connectivity requirements. By dividing the routing problem across multiple layers, each layer can be optimized for specific connection types, reducing the overall routing resources needed in any single layer and minimizing the total chip area required for routing.
2Reliability
If additional routing resources are allocated, then connectivity between cells is improved, but power consumption and chip area increase
Solution Approach 1:
By enabling vertical routing through multiple metal layers, the patent reduces the lateral distance that signals must travel across the chip. Shorter routing paths reduce resistive losses and capacitive loading, thereby reducing power consumption while maintaining or improving connectivity between cells.
Solution Approach 2:
The patent performs preliminary organization of IO patterns across multiple metal layers during the design phase. This pre-planning allows for optimized routing paths that minimize the number of vias and routing segments required, reducing both the routing resources needed and the power consumption associated with signal transmission.
3Productivity
If IO patterns are distributed across multiple metal layers, then routing efficiency is improved, but design complexity increases
Solution Approach 1:
The patent establishes universal design rules and methodologies that can be applied across all metal layers for IO pattern distribution. By creating a standardized approach that works consistently across M0, M1, M2, and higher layers, the patent simplifies the design process despite the increased number of layers, allowing designers to use the same principles and tools for multi-layer routing planning.
Solution Approach 2:
The patent changes the parameter of IO pattern distribution from a single-layer approach to a multi-layer approach, with specific rules for each metal layer. This parameter change enables more flexible and efficient routing by allowing IO patterns to be placed in the most appropriate layer based on their connectivity requirements, thereby improving routing efficiency while managing design complexity through systematic rules.
Data Source
AI summary
An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.