Automated IC Cell Layout Verification via IP Tag Scanning
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Solution Overview
Problem
Semiconductor manufacturing companies face challenges in scanning and verifying intellectual property (IP) tags in integrated circuit designs, particularly in SRAM layouts, due to duplication of cells and modifications that render IP tags unreadable, leading to time-consuming and inaccurate manual verification processes.
Innovation Solution
A system and method that embeds inert tags in the cell library data, allowing for electronic scanning and comparison of customer designs against a 'golden bits' reference to identify and verify IP usage, detect misuse, and ensure compliance with design rules, using a combination of design rule checking (DRC) and layout versus schematic (LVS) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual verification of IP tags is performed, then accuracy can be maintained, but time consumption increases significantly
Solution Approach 1:
The patent replaces manual mechanical verification processes with automated electronic scanning and comparison systems. The system automatically scans layout files for IP tags, extracts cell data, compares against reference libraries, and generates verification reports without human intervention, thereby eliminating time consumption while maintaining accuracy through computational precision
Solution Approach 2:
The patent creates digital copies of IP cell data and reference layouts that can be automatically compared. By storing reference cell information in databases and extracting corresponding cells from customer layouts, the system performs automated copying and comparison operations that are both accurate and time-efficient, replacing the need for manual verification of each IP instance
2Difficulty of detecting and measuring
If IP tags are made visible for scanning, then IP verification becomes possible, but design complexity increases
Solution Approach 1:
The patent applies local quality by making IP tags visible only in specific locations where they are needed for verification, rather than throughout the entire layout. The system scans for tags at specific positions within cells and only makes them prominent where IP verification is required, maintaining layout simplicity while enabling targeted IP detection
Solution Approach 2:
The patent introduces an intermediary scanning and comparison system that acts as a mediator between the layout files and the verification process. This intermediary system extracts IP tag information, compares it against reference data, and generates verification results, thereby enabling IP verification without requiring the layout itself to be complex or overly annotated
3Adaptability or versatility
If cell duplication is performed to extend SRAM size, then functionality is improved, but IP scanning becomes difficult
Solution Approach 1:
The patent applies segmentation by dividing the SRAM layout into individual cell units, each with its own IP tags. The verification system then scans and processes each segmented cell independently, allowing it to handle duplicated cells systematically. By segmenting the large SRAM structure into manageable cell-level units with identifiable tags, the system can accurately scan and verify IP usage even when cells are replicated to achieve different SRAM sizes
Data Source
AI summary
An automated system for checking an integrated circuit cell layout includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user.