Automatic Derivation of IC Cell Mapping Rules in ECO Flow

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Solution Overview

Problem

The existing engineering change order (ECO) flow for integrated circuit mapping is inefficient, requiring manual setup of numerous mapping rules and constraint checks, which is time-consuming and labor-intensive, especially in advanced nodes where complex cell placement and routing rules need to be satisfied.

Innovation Solution

The method involves generating bitmaps to represent mapping constraints for both ECO and PSC cells, allowing for bitwise logical operations to quickly determine compatibility, thereby automating the derivation and propagation of mapping rules, reducing setup time from weeks to minutes and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If manual setup of mapping rules and constraint checks is used, then mapping accuracy can be ensured, but the process becomes time-consuming and labor-intensive

Engineering Contradiction:
Improvemapping rule accuracyVSAvoidsetup time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent uses bitmap representations to copy and store mapping rules and constraints in a compact binary format. Each mapping rule and constraint is encoded as a bitmap, allowing rapid retrieval and comparison during ECO-PSC cell mapping without manual intervention, thus reducing setup time while maintaining accuracy

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent transforms mapping rules and constraints from human-readable formats into binary bitmap parameters. This parameter transformation enables efficient bitwise operations for rule verification, automatically checking compatibility between ECO cells and PSC fillers without manual rule setup, thereby reducing time loss while preserving mapping precision

Inventive Principle:
Principle #35Parameter changes

2Reliability

If comprehensive constraint checks are performed for ECO-PSC mapping, then mapping reliability is improved, but the complexity of the process increases

Engineering Contradiction:
Improvemapping reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple mapping constraints (routing track coloring alignment, power and ground pre-route conflicts, pin to PG spacing, via spacing) into unified bitmap representations. By combining these constraints into single bitmap structures, the system performs comprehensive reliability checks through simple bitwise operations, reducing process complexity while maintaining high mapping reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces bitmap representations as intermediary data structures between ECO cells and PSC fillers. These bitmaps serve as mediators that encode all mapping constraints, allowing automated compatibility verification through bitwise logical operations without requiring complex manual constraint checking, thus improving reliability while simplifying the overall process

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If multiple mapping constraints are checked for each cell pair, then compatibility accuracy is improved, but the runtime efficiency decreases

Engineering Contradiction:
Improvecompatibility check accuracyVSAvoidmapping speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent replaces traditional mechanical or manual constraint checking methods with bitwise logical operations on bitmap representations. Each mapping constraint is encoded in the bitmap, allowing simultaneous verification of multiple constraints (routing alignment, power/ground conflicts, spacing requirements) through single bitwise AND operations, thereby maintaining high compatibility check accuracy while dramatically improving mapping speed and productivity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Manufacturing precision

If detailed compatibility checks are performed, then mapping quality is improved, but the effort required increases

Engineering Contradiction:
Improvemapping qualityVSAvoidsetup effort
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent performs preliminary encoding of all mapping constraints into bitmap representations before the actual ECO-PSC mapping process. By pre-processing and storing constraints in bitmap format, the system eliminates the need for detailed manual compatibility checks during mapping, achieving high mapping quality through automated bitwise operations while significantly reducing setup effort

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11416661B2Automatic derivation of integrated circuit cell mapping rules in an engineering change order flow
Publication Date: 2022.08.16 SYNOPSYS INC
  • US11416661B2 patent drawing
  • US11416661B2 patent drawing
  • US11416661B2 patent drawing

AI summary

A method includes generating a first bitmap for a cell. The first bitmap is indicative of mapping constraints of the cell. The method also includes generating a second bitmap for a PSC filler cell. The second bitmap is indicative of the mapping constraints of the PSC filler cell. The method also includes a bitwise logical operation between a portion of the first bitmap and a respective portion of the second bitmap and determining a compatibility between the cell and the PSC filler cell based on at least a result of the bitwise logical operation.