Unassembled IC Cell Validation for MPL Coloring Conflicts
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Solution Overview
Problem
In the semiconductor industry, triple patterning lithography (TPL) coloring conflicts are complex to detect and correct, leading to time-consuming post-assembly adjustments, as they are classified as a NP-complete problem, and existing methods do not effectively prevent conflicts until IC cells are assembled.
Innovation Solution
A method and apparatus that perform a construction validation check on unassembled IC cells using rule-based design constraints to identify and adjust potential coloring violations, ensuring conflict-free assembly and eliminating the need for post-assembly color conflict checks by generating violation-free IC cells before assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-assembly color conflict checks are performed to detect TPL coloring conflicts, then coloring conflicts can be identified, but the process becomes time-consuming and complex due to the NP-complete nature of the problem
Solution Approach 1:
The patent performs construction validation checks on individual IC cells before assembly to identify and correct potential TPL coloring conflicts. By checking cells in isolation using rule-based constraints rather than waiting until post-assembly, the method prevents conflicts from occurring in the first place, eliminating the need for time-consuming post-assembly adjustments and complex NP-complete conflict detection algorithms
2Reliability
If construction validation checks are performed on unassembled IC cells using rule-based design constraints, then potential coloring violations can be identified and corrected before assembly, but additional processing steps are required during cell design
Solution Approach 1:
The patent divides the IC design into discrete cells, each of which is independently validated for TPL coloring conflicts using rule-based constraints. By segmenting the validation process at the cell level rather than attempting to validate the entire IC layout at once, the method simplifies the complexity while maintaining reliability - each cell can be checked and corrected independently before assembly
Solution Approach 2:
The construction validation check enables each IC cell to self-validate and self-correct potential coloring conflicts during the design phase. The rule-based constraints automatically identify violations within individual cells, allowing designers to correct issues before assembly without requiring complex external validation systems or post-assembly adjustments
Data Source
AI summary
The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.