Integrated Circuit Cell Placement and Routing via Timing Analysis
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Solution Overview
Problem
Conventional methods for designing integrated circuits separate the placement and routing of cells, leading to estimation errors and inefficiencies, as they do not account for actual wire information during placement, resulting in potential timing issues.
Innovation Solution
The method involves placing and routing cells along paths, where cells are placed after wires are routed, and timing analysis is used to select optimal locations, with cells at converging or diverging points being relocated to optimize slack and reduce congestion, and grouping cells in paths to prioritize critical timing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cells are placed before routing is performed, then placement can be completed independently, but timing accuracy deteriorates due to estimation errors
Solution Approach 1:
The patent merges the placement and routing operations into a unified process where routing information is obtained during placement. Specifically, the system performs routing for nets connected to cells being placed and uses this actual routing information to guide subsequent placement decisions, eliminating the need for separate estimation phases and improving timing accuracy while maintaining placement productivity.
Solution Approach 2:
The patent applies preliminary routing action before final cell placement. By performing routing for nets connected to seed cells and obtaining actual routing information in advance, the system can make informed placement decisions that account for actual wire delays rather than estimates, thereby improving timing accuracy without sacrificing placement efficiency.
2Device complexity
If placement is performed without actual routing information, then the process is simpler and faster, but estimation errors increase
Solution Approach 1:
The patent applies partial routing action selectively to nets connected to cells being placed, rather than performing complete routing for the entire design. This partial routing approach provides sufficient actual routing information to improve timing estimation accuracy without excessively increasing process complexity, as only the necessary routing information for current placement decisions is obtained.
Solution Approach 2:
The patent implements feedback by using actual routing information obtained during placement to guide subsequent placement decisions. The system continuously obtains routing results for nets connected to placed cells and uses this feedback to adjust placement strategies, improving timing estimation accuracy while managing process complexity through iterative refinement.
3Productivity
If cells are placed without considering actual wire information, then placement is more efficient, but routing congestion increases
Solution Approach 1:
The patent performs preliminary routing for nets connected to seed cells before finalizing cell placement. By obtaining actual routing information in advance, the system can identify congested areas and adjust placement decisions to avoid these regions, thereby reducing routing congestion while maintaining placement efficiency through informed decision-making.
Solution Approach 2:
The patent uses feedback from actual routing results to guide placement decisions. By continuously monitoring routing congestion through obtained routing information and adjusting placement strategies accordingly, the system reduces routing congestion without significantly impacting placement efficiency, as placements are made with knowledge of actual wire paths and congestion patterns.
Data Source
AI summary
Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.