Charge Dissipation Structures in IC Wiring Levels
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Solution Overview
Problem
Integrated circuits are prone to damage from electrostatic potential variations, electromagnetic interference, and electrostatic discharge during fabrication and operation, due to non-uniform electrical fields and plasma processes leading to charge deposition and arcing issues.
Innovation Solution
Incorporating electrically conductive charge dissipation structures within the integrated circuit chip, extending from the top surface of wiring levels to the substrate, dispersed between circuit structures to dissipate charge and reduce voltage gradients, while maintaining electrical isolation from circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma etch and plasma deposition processes are used during fabrication, then manufacturing capability is improved, but non-uniform charge deposition and electrostatic discharge damage occur
Solution Approach 1:
The patent applies preliminary action by forming conductive charge dissipation structures (such as polysilicon plugs or doped regions) in the dielectric layers before completing the plasma processing steps. These pre-formed structures provide predetermined charge dissipation paths that prevent charge accumulation during subsequent plasma etch and deposition operations, thereby protecting the circuit structures from ESD damage while maintaining manufacturing capability
Solution Approach 2:
The patent introduces intermediary conductive structures (charge dissipation paths formed by polysilicon plugs, doped regions, or conductive layers) that act as mediators between the plasma processing environment and the sensitive circuit structures. These intermediary structures intercept and dissipate charges generated during plasma processing before they can accumulate and cause damage to the circuits, thus enabling safe use of plasma processes
2Reliability
If charge dissipation structures are added to dissipate charge, then electrostatic discharge protection is improved, but device complexity increases
Solution Approach 1:
The patent merges the charge dissipation function with existing structural elements by forming conductive plugs within existing contact holes or via openings, and by using standard polysilicon deposition and doping processes that are already part of the fabrication flow. This integration approach adds ESD protection capability without requiring separate dedicated structures or processes, thereby limiting the increase in device complexity
Solution Approach 2:
The patent creates multi-functional conductive structures that serve both as charge dissipation paths and as part of the normal circuit interconnect structure. For example, polysilicon plugs formed in contact holes serve dual purposes: providing electrical connection for circuit operation and providing charge dissipation paths for ESD protection. This multi-functionality reduces the need for additional dedicated protection structures
3Reliability
If conductive structures extend through wiring levels, then charge dissipation capability is improved, but electrical isolation from circuit structures becomes difficult
Solution Approach 1:
The patent applies local quality by forming conductive charge dissipation structures only in specific localized regions where charge accumulation is most problematic, such as in dielectric layers between circuit levels or in specific contact holes. The conductive plugs are strategically positioned to provide charge dissipation paths in critical areas while leaving other regions isolated, thus achieving effective charge dissipation without requiring universal conductive structures throughout the entire device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces the risk of damage from electrostatic discharges and electromagnetic interference by dissipating charge and minimizing voltage gradients, enhancing the reliability and stability of integrated circuits during fabrication and operation.
Implementation Method 1
one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact
Data Source
AI summary
A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.