IC Chip At-Functional-Speed Testing Process Coverage
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Solution Overview
Problem
Current IC chip evaluation methods, such as at-functional-speed testing, fail to accurately predict the performance of IC chips under varying fabrication and operating conditions, as they only represent a small sampling of process and operation variations, and do not effectively determine the quality of test patterns or correlate manufacturing testing results with timing model accuracy.
Innovation Solution
The method involves running a statistical static timing analysis (SSTA) of a full IC chip design, creating at-functional-speed test (AFST) robust paths, re-running SSTA with a delay model setup based on these paths, calculating process coverage, and evaluating the IC chip based on this coverage to improve the accuracy of modeling and testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If at-functional-speed testing is performed on IC chips, then functionality and performance verification is achieved, but the test results only represent a small sampling of overall fabrication process and operation condition variations
Solution Approach 1:
The patent applies preliminary action by performing statistical static timing analysis (SSTA) before actual at-functional-speed testing to identify and prioritize critical paths. This preliminary analysis creates a roadmap for testing that anticipates which paths are most likely to fail under process variations, allowing the test to focus resources on high-risk areas rather than randomly sampling paths. The SSTA establishes delay models and identifies critical paths in advance, making the subsequent physical testing more effective and comprehensive.
Solution Approach 2:
The patent employs parameter changes by utilizing statistical timing analysis that incorporates process variation parameters (such as transistor threshold voltage, channel width, channel length variations) to evaluate timing paths. Instead of using fixed nominal values, the analysis varies these parameters according to their statistical distributions to predict how process variations will affect timing. This allows the testing to account for a broader range of process conditions without physically testing every possible variation.
2Reliability
If comprehensive testing of all possible process variations is performed, then complete process coverage is achieved, but the testing complexity and resource requirements increase drastically
Solution Approach 1:
The patent applies segmentation by dividing the complex timing analysis problem into manageable components: (1) identifying individual timing paths through the circuit, (2) analyzing delay elements along each path, (3) evaluating process variations affecting each delay element, and (4) aggregating results to determine overall path timing. This segmentation transforms an intractable problem of analyzing all possible process variations into a systematic procedure that can be automated and scaled to large circuits.
Solution Approach 2:
The patent applies partial action by focusing testing efforts on the most critical timing paths identified through statistical analysis, rather than attempting to test all possible paths equally. The SSTA identifies a subset of paths that are statistically most likely to be affected by process variations and fail timing requirements. By concentrating testing resources on these critical paths, the methodology achieves sufficient process coverage without the prohibitive complexity of exhaustive testing of all paths under all possible variation conditions.
3Ease of manufacture
If at-functional-speed tests are applied using static timing analysis with single worst case process point, then testing simplicity is maintained, but timing model accuracy is insufficient
Solution Approach 1:
The patent applies feedback by using the results of statistical static timing analysis to refine and update the timing models used in at-functional-speed testing. The SSTA provides feedback about which paths are critical and how they respond to process variations, which then informs the selection and configuration of test patterns. This feedback loop allows the testing methodology to adapt to the actual circuit behavior and process variations observed, improving timing model accuracy while maintaining the simplicity of static timing analysis-based testing.
Data Source
AI summary
Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.