IC Chip Carrier Alignment for Stress Testing

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Solution Overview

Problem

The challenge lies in testing and handling of small, thin integrated circuit (IC) chips, which are prone to damage due to their fragile nature and the complexity of manufacturing and testing processes, especially when numerous ICs are packed densely in a silicon wafer, making it difficult to apply stress conditions without causing further damage.

Innovation Solution

A method and apparatus involving a chip carrier with a rigid structure and alignment features that affix and align IC chips on an adhesive substrate, allowing for stress testing while protecting the chips and enabling automated probing to assess their responsiveness to various conditions such as heat and mechanical stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If IC chips are made smaller to increase the number of devices per wafer area, then productivity increases, but the chips become more fragile and prone to damage during handling and testing

Engineering Contradiction:

Improvenumber of IC chips per wafer areaVSAvoidchip integrity during handling

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the wafer into individual chip segments that remain connected through the carrier board, allowing each chip to be tested independently while maintaining structural support from the carrier system

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a carrier board as an intermediary structure between the chips and the testing equipment. This carrier board provides mechanical support and protection to fragile chips while enabling automated probing and stress condition application

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If additional stress conditions are applied to test chip reliability, then measurement precision improves, but the risk of damaging fragile chips increases

Engineering Contradiction:

Improvechip responsiveness assessmentVSAvoidchip damage during stress testing

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies protective coating layers to the chip surfaces before stress testing begins. These protective layers cushion the chips against damage from mechanical stress, thermal cycling, and other harsh testing conditions while still allowing accurate measurement of chip performance

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Ease of operation

If automated probing is implemented to reduce handling damage, then ease of operation improves, but alignment precision becomes more critical and difficult to achieve

Engineering Contradiction:

Improveautomated testing capabilityVSAvoidprobe-to-contact alignment

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The patent designs the carrier board with universal alignment features and standardized contact patterns that work across different chip types and testing scenarios. This universality simplifies the automated probing process by providing consistent reference points for alignment while maintaining high precision through the rigid carrier structure

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10177021B2Integrated circuits and methods therefor

Publication Date: 2019.01.08 NXP BV

AI summary

Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.