Integrated Circuit Chip Compression Mapping Neural Network Efficiency
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Solution Overview
Problem
Existing neural network processing systems rely on CPUs or GPUs, leading to high power consumption and inefficient computation due to the need for extensive data transmission and processing.
Innovation Solution
An integrated circuit chip device with a primary processing circuit and multiple basic processing circuits, where each basic processing circuit includes a compression mapping circuit to compress data, reducing transmission and computation resources by controlling data compression based on operation requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural network operations are performed using CPU or GPU, then computation can be implemented, but power consumption is high and processing efficiency is low
Solution Approach 1:
The processing system is segmented into a primary processing circuit and multiple basic processing circuits arranged in a tree structure. The primary processing circuit performs operations on input data and transmits results to basic processing circuits, which then perform subsequent operations. This segmentation allows parallel processing across multiple circuits, improving productivity while distributing power consumption across the segmented architecture.
Solution Approach 2:
The patent transitions from traditional CPU/GPU sequential processing to a multi-dimensional tree-structured circuit architecture. Basic processing circuits are arranged in hierarchical levels with multiple branches, enabling simultaneous operations across different branches and levels. This dimensional change from linear to tree-structured processing improves computational efficiency and throughput.
2Productivity
If data is transmitted extensively between processing units, then neural network operations can be performed, but transmission resources and computation overhead increase
Solution Approach 1:
The primary processing circuit performs preliminary operations on input data before transmitting to basic processing circuits. Additionally, compression mapping circuits perform preliminary compression on data before transmission occurs. This preliminary action reduces the volume of data that needs to be transmitted across the network, decreasing transmission overhead while maintaining computational throughput.
Solution Approach 2:
Compression mapping circuits extract and remove redundant information from data before transmission. By taking out unnecessary data elements and compressing the remaining information, the system reduces transmission volume while preserving the essential data needed for neural network operations, thereby improving the ratio of useful computation to transmission overhead.
Data Source
AI summary
The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.