IC Chip Connectivity Test via Signal Combination and Reset Control
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Solution Overview
Problem
Conventional boundary scan tests for integrated circuit chips are time-consuming and inefficient, particularly when testing the electrical connection state of multiple pads in memory devices, requiring a more stable and rapid connectivity testing scheme.
Innovation Solution
An integrated circuit chip design that includes a test enable pad, signal combination unit, test output pads, and a reset control unit to generate system reset signals, enabling a connectivity test by internally activating a reset signal and ensuring stable operation during the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan test is used to test electrical connection state of pads, then testing can be performed, but significant time is required making the test time-consuming
Solution Approach 1:
The chip is divided into multiple functional regions with dedicated test input pads and test output pads. The signal combination unit segments the testing function by combining signals from multiple test input pads and generating corresponding test output signals, enabling parallel testing of multiple pads simultaneously rather than sequential boundary scan testing
Solution Approach 2:
A reset control unit is implemented to activate a system reset signal before the connectivity test begins. This preliminary action ensures that the integrated circuit chip is in a known stable state with all internal circuits properly initialized, preventing testing errors due to undefined circuit states and eliminating the need for repeated tests
2Productivity
If parallel connectivity test scheme is implemented, then testing speed is improved, but stable operation during testing requires specialized chip design
Solution Approach 1:
The signal combination unit serves multiple functions: it combines signals from test input pads for parallel connectivity testing, and can also work with the reset control unit to provide stable operation during testing. The test input pads and test output pads are integrated into the existing pad structure, allowing the same physical infrastructure to support both normal operation and enhanced parallel testing functionality
Solution Approach 2:
The reset control unit acts as an intermediary between the test enable signal and the internal circuits. It receives the test enable signal and automatically generates the system reset signal, mediating the transition to a stable test state without requiring complex external control logic. This intermediary component simplifies the overall system design by centralizing the reset control function
Data Source
AI summary
An integrated circuit chip includes a test enable pad configured to receive a test enable signal, a plurality of test input pads including a reset pad, a signal combination unit configured to combine signals input to the plurality of test input pads when the test enable signal is activated, and to generate a plurality of test output signals, a plurality of test output pads configured to output the plurality of test output signals, and a reset control unit configured to generate a system reset signal using a signal input to the reset pad when the test enable signal is deactivated, and to generate the system reset signal using the test enable signal when the test enable signal is activated.