3D Stacked IC Chip With Dummy Bump For Stress Relief
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Solution Overview
Problem
There is a challenge in developing miniaturized electronic devices that maintain a small form factor and high reliability without increasing size, particularly in integrating multiple IC functions effectively.
Innovation Solution
The solution involves a three-dimensionally stacked IC chip structure with via contact plugs, dummy bump structures, and bump structures made of the same material, which includes a substrate, device layers, and conductive liners, allowing for improved electrical connectivity and physical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple IC functions are integrated in a planar layout, then device functionality is improved, but device area increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking, where multiple IC chips are vertically stacked and interconnected through through-holes. This dimensional change allows multiple functional ICs to be integrated without increasing the footprint area, as the functionality is expanded in the vertical dimension rather than lateral expansion
2Reliability
If through holes are formed to pass through substrates for vertical connectivity, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple manufacturing operations into integrated process steps. The through-hole formation, via contact plug deposition, and connection pad liner formation are performed as part of a unified manufacturing sequence, reducing the number of separate process modules and simplifying overall manufacturing complexity while maintaining vertical connectivity
3Reliability
If contact structures are formed inside through holes, then electrical connectivity between stacked ICs is improved, but contact resistance increases
Solution Approach 1:
The patent employs composite contact structures consisting of multiple material layers including via contact plugs, connection pad liners, and bump structures. These composite structures combine materials with different properties to achieve both low contact resistance and mechanical reliability, with each layer contributing specific electrical or mechanical functions to reduce overall contact resistance
4Area of stationary object
If IC chips are stacked vertically to reduce footprint, then device area is reduced, but tolerance to physical stress decreases
Solution Approach 1:
The patent incorporates dummy bump structures and reinforced connection pad liners that serve as mechanical buffers and stress-distributing elements. These structures are positioned to absorb and distribute physical stress before it reaches critical connection points, providing beforehand cushioning that protects the vertically stacked IC configuration from mechanical failure
Data Source
AI summary
An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.