IC Chip Package Cover Profile and Adhesive Control
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Solution Overview
Problem
Conventional IC chip packages face challenges in controlling adhesive application, leading to potential gaps or overflow, which can result in reduced reliability and quality due to moisture penetration or insulating coatings, and exposed through holes prone to oxidation and contamination, affecting electrical connections.
Innovation Solution
The IC chip package design includes a substrate with conductive vias filled with material to connect solder pads, bonding wires connecting the chip and substrate, and a cover with a smaller profile that leaves a peripheral area uncovered, using adhesive means on the wires and cover edges to secure and seal the package, preventing adhesive overflow and protecting the vias from ambient air.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If adhesive means is applied to secure the cover to the substrate, then the cover adheres to the substrate, but the adhesive may overflow down along the through holes to form insulating coatings that prevent proper electrical connection
Solution Approach 1:
The substrate is divided into a covered area (where the cover is placed) and an uncovered peripheral area. This segmentation allows adhesive to be applied in controlled zones: some adhesive secures the cover while other adhesive in the uncovered area prevents overflow down the through holes, maintaining electrical connection reliability.
Solution Approach 2:
Different regions of the substrate have different functions: the covered area provides structural support and alignment, while the uncovered peripheral area serves as an adhesive barrier zone. This local differentiation of function allows the adhesive to perform its bonding function without overflowing into the through holes.
2Strength
If adhesive means is applied to secure the cover to the substrate, then the cover adheres to the substrate, but tiny gaps may form between the cover and substrate allowing moisture penetration that adversely affects chip functioning
Solution Approach 1:
The uncovered peripheral area is prepared in advance as an adhesive application zone. This preliminary structural design ensures that when adhesive is applied, it has a designated path and barrier zones, preventing both insufficient adhesion (gaps) and excessive adhesion (overflow), thereby sealing against moisture penetration.
3Ease of manufacture
If through holes are exposed to ambient air, then the substrate can be manufactured with simple processes, but the through holes are liable to be affected by oxidation or contamination leading to faulty electrical connection
Solution Approach 1:
The through holes are extracted from the ambient environment by placing them under the cover in a protected receiving chamber. This removes the through holes from exposure to oxidizing and contaminating ambient air, while the uncovered peripheral area still allows for simple manufacturing processes.
Data Source
AI summary
An IC (integrated circuit) chip package includes a substrate (2), a chip (3), a plurality of bonding wires (32), and a cover (5). The substrate has a top surface, a bottom surface, a receiving chamber (23) defined therein, a plurality of solder pads (24) arranged around the top surface and the bottom surface, and a plurality of vias (25) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate to cover the opening, and has a smaller profile than that of the substrate, thereby not cover a peripheral area of the top surface.