IC Chip Reverse Engineering Prevention via Signal Routing Shift Register
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Solution Overview
Problem
Integrated circuit chips are vulnerable to reverse engineering attacks, which compromise security structures, particularly in smart cards, due to advancements in probing technology, and existing methods to prevent these attacks either increase the chip size or manufacturing costs.
Innovation Solution
An integrated circuit chip design that includes a signal generator, metal line part, comparison logic part, and signal routing part, where the signal routing part is a shift register, allowing for increased security without increasing the chip size by detecting external invasions through signal comparison and generating appropriate responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate protective layer is added to the silicon chip surface to prevent probe attacks, then security level is improved, but manufacturing cost and manufacturing difficulty increase
Solution Approach 1:
The patent merges the protective function with existing chip structures by utilizing metal lines and routing regions that are already part of the chip design. Instead of adding a separate protective layer, the invention combines security features with the functional interconnect structures, making the metal lines serve both signal transmission and protection purposes simultaneously.
Solution Approach 2:
The patent makes the metal lines and routing regions serve multiple functions: they act as both functional interconnects for signal transmission and as protective structures against probe attacks. The same structures that connect circuit components also provide security by detecting probing attempts, eliminating the need for dedicated protective layers.
2Reliability
If a separate protective layer is added to the silicon chip surface to prevent probe attacks, then security level is improved, but chip size increases
Solution Approach 1:
The protective structures are merged with the existing metal lines and routing regions, so no additional area is required. The security features are implemented within the space already allocated for functional interconnects, preventing any increase in chip size while still providing protection against probe attacks.
3Reliability
If metal lines are placed more densely to prevent probe attacks, then security level is improved, but routing area increases
Solution Approach 1:
The patent applies different properties to different parts of the metal line structure. Certain metal lines are configured with specific characteristics (such as being positioned in accessible routing regions and connected to detection circuits) to provide protection, while other metal lines maintain their functional interconnect properties. This localized differentiation allows security features to be integrated without requiring overall densification of all metal lines.
Data Source
AI summary
An integrated circuit chip with reverse engineering prevention includes: a signal generator part configured to generate a first signal; a metal line part configured to receive the first signal generated at the signal generator part and generate a second signal; a comparison logic part configured to compare the first signal generated at the signal generator part and the second signal generated at the metal line part; and a signal routing part formed on both sides of the metal line part to connect the signal generator part with the metal line part at one side and connect the metal line part with the comparison logic part at the other side, where the signal routing part is a shift register.