Integrated Circuit Chip Test Pad Buffering for Connectivity Testing
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Solution Overview
Problem
Conventional connectivity testing of integrated circuit chip pads is time-consuming due to the use of boundary scan tests, which require shifting test patterns, and recent parallel signal testing schemes for memory devices need improved chip designs to support stable and efficient connectivity testing.
Innovation Solution
The integration of single-ended and differential-type buffers in an integrated circuit chip, optimized for use based on test mode, to reduce current consumption and enable quick and stable electrical connection state testing of multiple pads, with a signal combination unit generating test output signals for connectivity testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan test is used to test bonding state of board and pins, then testing can be performed, but test time becomes much longer
Solution Approach 1:
The patent segments the testing function by introducing dedicated test input pads and test output pads separate from normal operation pads. The test circuit is divided into distinct components: test input pads for receiving test signals, buffers for signal conditioning, and test output pads for providing test results. This segmentation enables independent test operations without affecting normal device functionality and allows parallel testing of multiple connections simultaneously.
Solution Approach 2:
The patent introduces buffers as intermediary components between test input pads and test output pads. These buffers act as mediators that condition and transmit test signals through the device under test. The single-ended buffers and differential buffers serve as intermediate signal processing stages that enable reliable test signal transmission while isolating the test circuit from the core device logic.
2Productivity
If parallel signal testing scheme is used to test electrical connection state of pads, then test time is reduced, but chip design complexity increases
Solution Approach 1:
The patent implements universal test pads that can serve dual purposes: normal operational pads for device functionality and test pads for connectivity testing. The test input pads and test output pads are designed to work with the existing pad structure, allowing the same physical infrastructure to support both normal operation and testing functions. This multi-functionality reduces the need for entirely separate test infrastructure.
Solution Approach 2:
The patent changes the operational parameters of existing pads by introducing test modes that alter how pads function. During normal operation, pads perform their intended functions. During testing, the same pads can be reconfigured through parameter changes (mode switching) to serve as test signal paths. This parameter-based flexibility allows parallel testing without permanently increasing structural complexity.
3Loss of energy
If single-ended type buffers are used in connectivity test mode, then current consumption is reduced, but signal integrity may be compromised
Solution Approach 1:
The patent implements dynamic buffer selection that adapts to different operating modes. The system can switch between single-ended buffers and differential buffers based on the operational context. In connectivity test mode, single-ended buffers are used for lower power consumption. In normal operation mode or when signal integrity is critical, differential buffers can be activated. This dynamic adaptation allows the system to optimize between power consumption and signal integrity based on real-time requirements.
Solution Approach 2:
The patent applies different buffer types in different locations and contexts within the circuit. Single-ended buffers are used specifically in connectivity test paths where power consumption is a concern, while differential buffers are used in normal operation paths where signal integrity is paramount. This localized application of different buffer qualities allows each part of the circuit to have the optimal characteristics for its specific function.
Data Source
AI summary
An integrated circuit chip includes a plurality of test input pads configured to receive a plurality of test input signals, a plurality of single-ended type buffers configured to receive signals input to the plurality of test input pads in a connectivity test mode, a plurality of differential-type buffers configured to receive signals input to the plurality of test input pads in a normal mode, a signal combination unit configured to combine the plurality of test input signals input through the plurality of single-ended type buffers, and to generate a plurality of test output signals, and a plurality of test output pads configured to output the plurality of test output signals in the connectivity test mode.