Integrated Circuit Chip Via Fabrication Without Passivation
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Solution Overview
Problem
The existing methods for fabricating integrated circuit chips with electrical connection vias are complex due to the use of a permanent passivation layer, which cannot completely fill the central holes and is prone to internal oxidation, leading to inefficiencies in the production process.
Innovation Solution
A method involving physical vapor phase deposition and electrochemical deposition to create conductive layers and pillars, followed by selective chemical deposition of a protective layer, which simplifies the process and eliminates the central blind hole, using copper for conductive materials and a cobalt-tungsten-phosphorous alloy for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a permanent passivation layer is used to cover the rear face and vias, then protection against oxidation is provided, but the fabrication process becomes complex and the central holes cannot be completely filled
Solution Approach 1:
The invention removes the permanent passivation layer from the fabrication process entirely. Instead of using a photosensitive polymer passivation layer that requires multiple processing steps and cannot completely fill central holes, the patent uses a simplified approach where copper layers are deposited directly and selectively removed to form vias and pillars, eliminating the need for passivation layer deposition, patterning, and etching steps
Solution Approach 2:
The invention inverts the traditional approach by not trying to protect the rear face with a passivation layer, but instead by carefully controlling the deposition and removal of copper layers to form the electrical connection structures directly, allowing the copper itself to define the via and pillar structures without requiring a protective passivation layer
2Reliability
If a permanent passivation layer is used, then some protection is provided, but internal oxidation risk remains and the process requires many steps
Solution Approach 1:
The invention applies preliminary protective action by depositing a thin copper layer on the rear face before forming the via structures. This initial copper layer serves as a protective barrier against oxidation during subsequent processing steps, eliminating the need for a separate passivation layer while preventing internal oxidation of the vias
Solution Approach 2:
The invention uses temporary copper layers that are deposited and then selectively removed (discarded) to form the via structures. The copper is deposited as a continuous layer, then patterned and etched away in specific areas to create the vias and pillars, with the remaining copper forming the final electrical connection structures
3Reliability
If the passivation layer is used to cover vias, then protection is provided, but the central hole filling is incomplete
Solution Approach 1:
The invention uses partial action by depositing copper layers to specific thicknesses and in specific areas rather than attempting to completely fill all holes. The copper is deposited to form the via walls and pillar structures, with the deposition thickness and area carefully controlled to create the desired electrical connection structures without requiring complete hole filling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the complexity of the fabrication process, prevents internal oxidation, and ensures complete filling of the holes, resulting in reliable and corrosion-resistant electrical connections.
Implementation Method 1
producing, by a physical vapor phase deposition (PVD), a thin layer made of an electrically conductive material
Implementation Method 2
producing, by a local electrochemical deposition with electrical contact on said thin layer, a thick local layer made of an electrically conductive material
Implementation Method 3
producing, by a selective chemical deposition, a local external protection layer at least partly covering the electrical connection via and the rear electrical connection pillar
Data Source
AI summary
An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.