IC Clock Frequency Handshake for Dynamic Performance Points
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Solution Overview
Problem
Existing systems with multiple integrated circuits face challenges in dynamically adjusting the transport clock frequency and voltage between them, as these parameters are often fixed by protocols, limiting flexibility in power management and performance optimization.
Innovation Solution
A method and system that allow integrated circuits to detect a need to change their operating performance point, adjust voltage and maximal receiver clock frequency, and communicate these changes to other ICs, enabling dynamic adjustment of transmit clock frequencies and acknowledgments to ensure compliance with new operating performance points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transport clock frequency is fixed by protocol between integrated circuits, then interoperability and reliability are improved, but adaptability and power management flexibility deteriorate
Solution Approach 1:
The patent implements dynamic adjustment of the transport clock frequency by introducing a clock frequency adapter that can modify the frequency based on operating performance point changes. The system dynamically selects from multiple clock frequency values (e.g., 480 MHz, 240 MHz, 120 MHz) depending on the voltage level and performance requirements, allowing the fixed protocol constraint to be adapted to varying power and performance conditions.
2Use of energy by moving object
If the voltage and frequency of integrated circuits are adjusted dynamically, then power consumption is reduced, but compatibility with fixed-protocol transport clocks deteriorates
Solution Approach 1:
The patent introduces a clock frequency adapter as an intermediary component between the variable-frequency internal circuits and the fixed-frequency transport interface. This adapter receives the dynamically adjusted clock signal and conditionally modifies it to match the required transport clock frequency based on the current operating performance point, ensuring protocol compatibility is maintained even as internal voltage and frequency are adjusted for power efficiency.
3Productivity
If the maximal receiver clock frequency value is changed to match new operating performance points, then performance optimization is improved, but communication coordination with distant integrated circuits becomes more complex
Solution Approach 1:
The patent implements a feedback mechanism where the maximal receiver clock frequency value is exported to distant integrated circuits and acknowledgments are received. This feedback loop ensures that both communicating circuits are aware of each other's clock frequency capabilities and adjust accordingly, maintaining synchronization and avoiding communication errors while enabling performance optimization through dynamic frequency selection.
Data Source
AI summary
A method of changing an operating performance point of an integrated circuit including detecting a need to change the operating performance point of the integrated circuit to a new operating performance point. The method also includes changing a voltage of the integrated circuit to correspond with the new operating performance point, changing a maximal receiver clock frequency value to correspond with the new operating performance point, exporting the maximal receiver clock frequency value to a distant integrated circuit, and receiving an acknowledgement of the changed maximal receiver clock frequency value from the distant integrated circuit.