Dynamic Clock Frequency Scaling for IC Power Management
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Solution Overview
Problem
Existing methods for managing thermal design power (TDP) in integrated circuits are inadequate as they lead to overreactions and performance losses due to coarse-grained responses to power consumption changes, failing to dynamically adjust to real-time power consumption levels and handle both TDP violations and slacks effectively.
Innovation Solution
A dynamic power adjustor that scales the clock frequency of an integrated circuit based on real-time power consumption levels, adjusting the effective clock frequency to maintain optimal power consumption and performance by using a frequency scaling factor calculated from the difference between threshold and actual power consumption levels, and also adjusts voltage and I/O speed as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a rigid and static response is used when environmental conditions exceed a predefined threshold, then the system can be simplified and easier to control, but performance loss increases due to overreaction and coarse-grained power reduction
Solution Approach 1:
The patent implements dynamic power adjustment by continuously monitoring power consumption levels and adjusting the integrated circuit's power state in real-time based on current conditions rather than using fixed threshold-based responses. This allows the system to adapt granularly to changing conditions, avoiding the performance loss associated with coarse-grained static control while maintaining manageable complexity through automated feedback mechanisms.
2Device complexity
If discrete power settings are used with step-down responses to TDP violations, then the control mechanism is simplified, but performance loss increases due to the coarse-grained nature of the response
Solution Approach 1:
The patent changes the control parameter from discrete power settings to continuous power consumption level monitoring and adjustment. By tracking actual power consumption in real-time and making fine-grained adjustments to the integrated circuit's operating parameters, the system achieves precise control without the performance penalties of discrete step-down responses, while keeping the control mechanism manageable through automated algorithms.
3Device complexity
If non-deterministic analog measurements of environment conditions are used, then the measurement system is simpler, but system performance becomes inconsistent among different users
Solution Approach 1:
The patent replaces non-deterministic analog measurements with deterministic digital power consumption level monitoring. By using digital counters and registers to track power consumption in real-time with precise granularity, the system eliminates the inconsistency issues associated with analog measurements while maintaining manageable complexity through standard digital logic implementation. This substitution ensures that all users receive consistent, deterministic performance regardless of environmental variations.
4Productivity
If real-time power consumption monitoring and dynamic clock frequency scaling are implemented, then performance is optimized by minimizing unnecessary power reduction, but device complexity increases
Solution Approach 1:
The patent implements a feedback control mechanism where power consumption levels are continuously monitored and fed back to dynamically adjust the integrated circuit's clock frequency and power state. This closed-loop system optimizes performance by making real-time adjustments based on actual power consumption rather than using static thresholds, while managing complexity through automated feedback algorithms that eliminate the need for complex manual control logic.
Data Source
AI summary
Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.