Integrated Circuit Clock Gapping for Power Reduction
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Solution Overview
Problem
Integrated circuits (ICs) face increasing power consumption, leading to higher cooling needs and additional electrical power usage, which necessitates a reduction in power consumption to mitigate environmental and utility costs.
Innovation Solution
Implementing clock gapping by introducing controller-determined gaps in clock signals to circuit blocks based on performance factors and external conditions, such as temperature and data rate, to reduce the effective clock rate and subsequently lower power consumption, while shims facilitate communication between blocks with different clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are continuously provided to all circuit blocks, then data communication and processing are maintained, but electrical power consumption increases
Solution Approach 1:
The patent divides the integrated circuit into multiple independent circuit blocks (first circuit block, second circuit block, etc.), each capable of receiving independently gapped clock signals. This segmentation allows selective power management where each block can be independently put into low-power states when not actively processing data, thereby reducing overall power consumption while maintaining communication capability when needed
Solution Approach 2:
The patent implements periodic clock gapping by introducing variable gap periods between clock pulses to different circuit blocks. When a circuit block is not actively processing data, the clock signal is gapped (reducing frequency or stopping temporarily), and when data processing is required, the clock signal resumes. This periodic activation based on actual need reduces power consumption while maintaining productivity when required
2Use of energy by moving object
If clock rate is reduced to lower power consumption, then electrical power consumption decreases, but data processing speed and communication efficiency are compromised
Solution Approach 1:
The patent employs dynamic clock gapping where the gap parameters (gap count, gap period) are variable and can be adjusted in real-time based on the operational state of each circuit block. When a block requires high-speed processing, the clock gap is reduced or eliminated; when the block is idle or performing low-priority operations, the clock gap is increased to reduce power consumption. This dynamic adjustment resolves the contradiction by adapting the clock rate to actual processing needs
Solution Approach 2:
The patent changes the temporal parameters of clock signals (frequency, gap duration, gap count) based on the operational requirements of different circuit blocks. By varying these parameters dynamically, the system can achieve low power consumption during idle periods while maintaining high processing speeds when data communication and processing are required, thus resolving the speed-power contradiction
3Ease of operation
If different clock rates are applied to different circuit blocks for power management, then independent power control is achieved, but data communication between blocks with different clock rates becomes complex
Solution Approach 1:
The patent introduces shim components as intermediaries between circuit blocks operating at different clock rates. These shims act as buffer and synchronization mechanisms that translate data between blocks with different clock gapping configurations. The shim absorbs clock rate differences and ensures proper data timing, thereby enabling independent power management of different blocks without creating complex communication synchronization problems
Data Source
AI summary
A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.