IC Clock Synchronization Using Reassigned Memory Pins
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Solution Overview
Problem
Existing methods for synchronizing signal timing between integrated circuit components in electronic systems are inefficient, leading to timing errors and increased power consumption, particularly in memory components, and do not fully comply with industry standards.
Innovation Solution
A method and system that utilize a dedicated clock and data recovery (CDR) pin on a controlling IC to monitor and adjust clock timing with external memory components, allowing for accurate synchronization without adding circuitry or power consumption to the memory devices, and reconfiguring existing pins to perform timing synchronization tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing circuitry and logic are added to memory components to minimize timing errors, then timing accuracy is improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the clock and data recovery function from the memory component and places it in the controlling IC. The memory component only needs to return data through existing pins, while the controlling IC performs the complex timing recovery operations, reducing the memory component's circuitry and power consumption while maintaining timing accuracy
Solution Approach 2:
The patent makes existing memory pins multi-functional by using them for both data transmission and clock synchronization. The REFD pin, originally dedicated to reference voltage, is repurposed to carry clock recovery data, eliminating the need for dedicated synchronization pins and reducing overall system complexity
2Measurement precision
If timing circuitry and logic are added to memory components to minimize timing errors, then timing accuracy is improved, but chip area increases
Solution Approach 1:
The patent extracts the clock and data recovery function from the memory component and places it in the controlling IC. The memory component only needs to return data through existing pins, while the controlling IC performs the complex timing recovery operations, reducing the memory component's circuitry and power consumption while maintaining timing accuracy
Solution Approach 2:
The patent makes existing memory pins multi-functional by using them for both data transmission and clock synchronization. The REFD pin, originally dedicated to reference voltage, is repurposed to carry clock recovery data, eliminating the need for dedicated synchronization pins and reducing overall system complexity
3Reliability
If existing methods for synchronizing signal timing are used, then timing synchronization is achieved, but power consumption increases and timing accuracy decreases
Solution Approach 1:
The patent implements a self-service mechanism where the memory component automatically returns data that encodes timing information, and the controlling IC independently extracts and uses this information for clock synchronization. This eliminates the need for additional active synchronization circuits in the memory component, reducing power consumption while maintaining reliable timing synchronization
Solution Approach 2:
The patent establishes a feedback loop where the controlling IC sends test patterns to the memory component, receives returned data with embedded timing information, and uses this feedback to continuously adjust and optimize clock synchronization, improving both accuracy and efficiency
4Measurement precision
If dedicated pins are added for clock and data recovery, then timing synchronization accuracy is improved, but device complexity and routing complexity increase
Solution Approach 1:
The patent makes existing memory pins multi-functional by using them for both data transmission and clock synchronization. The REFD pin, originally dedicated to reference voltage, is repurposed to carry clock recovery data, eliminating the need for dedicated synchronization pins and reducing overall system complexity
Solution Approach 2:
The patent merges the clock synchronization function with the existing data transmission pathway. By encoding timing information within the data return path and using existing pins for dual purposes, the patent combines multiple functions into unified pathways, reducing the number of required pins and simplifying routing
Data Source
AI summary
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.