IC Clock Recovery and Phase Alignment Without Extra PLLs
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Solution Overview
Problem
In integrated circuits, particularly in master/slave configurations, achieving synchronization of reference clocks between devices is challenging, leading to higher jitter and the need for additional phase-locked loop (PLL) circuits, especially when using asynchronous clock protocols like DisplayPort, which complicates communication and increases hardware requirements.
Innovation Solution
The implementation of a circuit that includes a divider circuit, a recovery circuit, and a phase aligner circuit to receive and align a preamble signal, allowing the integrated circuit to operate without an extra clock signal or additional PLL circuit, enabling two-way communication by locking the phase of the IC to the external component's reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous clock protocols (e.g., DisplayPort) are used for communication between master and slave devices, then protocol compatibility is achieved, but jitter increases and additional PLL circuits are required on the slave device
Solution Approach 1:
The invention extracts the clock signal from the data stream using clock data recovery (CDR) circuitry, separating the clock function from dedicated clock pins. This eliminates the need for external clock inputs and associated PLL circuits on the slave device, reducing hardware complexity while maintaining asynchronous protocol compatibility
Solution Approach 2:
The data stream serves multiple functions: it carries both data and embedded clock information. By encoding the clock signal within the data stream itself, the same transmission medium performs dual roles, eliminating the need for separate clock infrastructure and reducing overall system complexity
2Reliability
If synchronous clock protocols are used for communication between master and slave devices, then jitter tolerance improves, but dedicated clock pins and PLL circuits are still required on the slave device
Solution Approach 1:
The invention extracts the clock signal from the data stream using CDR circuitry, eliminating the need for dedicated clock pins and external clock sources. This approach achieves synchronous-like reliability through embedded clock recovery without requiring the complex external clock infrastructure
Solution Approach 2:
The CDR circuit acts as an intermediary that recovers the clock signal from the data stream, mediating between the asynchronous physical layer and the synchronous internal logic. This embedded clock recovery provides jitter tolerance similar to synchronous protocols without requiring dedicated clock pins or external PLL circuits
3Stability of the object's composition
If dedicated clock pins and PLL circuits are added to the slave device, then clock synchronization is achieved, but device complexity and hardware requirements increase
Solution Approach 1:
The invention extracts the clock signal directly from the incoming data stream using CDR circuitry, eliminating the need for dedicated clock pins and external clock sources. This maintains clock synchronization functionality while significantly reducing the hardware required for clock management
Solution Approach 2:
The slave device generates its own clock signal by recovering it from the incoming data stream, making the system self-sufficient. The CDR circuit continuously locks onto the embedded clock signal, providing automatic synchronization without external intervention or additional clock infrastructure
Data Source
AI summary
Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.