IC Timing Optimization via Clock Skew Scheduling
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Solution Overview
Problem
Existing IC design optimization techniques, such as retiming, face limitations due to changes in netlist topology, making it difficult to maintain correlation with original designs and debug issues, as they alter the position of clocked elements relative to combinational logic elements.
Innovation Solution
A method that expresses IC design as a graph, identifies paths with clocked and computational elements, and optimizes timing by skewing clock signals without moving clocked elements, presenting simulation results as clock skew scheduling to maintain original design topology and facilitate debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If retiming is used to optimize timing performance, then timing optimization is improved, but netlist topology changes making debugging difficult
Solution Approach 1:
The patent creates a retimed copy of the netlist for timing optimization while preserving the original netlist topology for debugging purposes. The simulation system can switch between viewing results in the original topology or the retimed topology, allowing timing optimization to be applied without permanently altering the design structure or making debugging difficult.
2Manufacturing precision
If clocked elements are moved for retiming, then timing performance is improved, but correlation with original design is lost
Solution Approach 1:
The patent generates a retimed copy of the netlist where clocked elements are moved for timing optimization, while maintaining the original netlist unchanged. This allows timing performance improvement without losing correlation to the original design, as both versions coexist and can be referenced independently.
Solution Approach 2:
The patent separates the netlist into multiple representations: the original unretimed netlist and one or more retimed copies. This segmentation allows each version to serve its specific purpose - the original for design correlation and debugging, and the retimed copies for timing optimization analysis.
3Ease of operation
If traditional clock skew scheduling is used, then timing optimization is limited, but design topology remains unchanged
Solution Approach 1:
The patent overcomes the limitation of traditional clock skew scheduling by creating retimed copies of the netlist where clocked elements can be freely moved. This copying approach enables more aggressive timing optimization beyond what traditional skew scheduling allows, while the original topology remains preserved for reference.
Data Source
AI summary
A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design.