Reconfigurable IC Configuration Manager Circuit Reduces Latency

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Solution Overview

Problem

Current reconfigurable hardware technologies, such as FPGAs and CGRAs, face significant challenges with lengthy reconfiguration times, which hinder their ability to adapt quickly to changing workloads and real-time applications.

Innovation Solution

The proposed solution involves an Integrated Circuit (IC) device with a configuration manager circuit that efficiently reconfigures processing elements by utilizing configuration memory elements to store multiple settings and rapidly switch between them, allowing for simultaneous reconfiguration of multiple processing elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional reconfiguration methods are used in FPGAs and CGRAs, then flexibility and adaptability are improved, but reconfiguration time increases significantly

Engineering Contradiction:
ImproveflexibilityVSAvoidreconfiguration time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent pre-loads configuration data into on-chip memory elements before reconfiguration is needed. Configuration data is prepared and stored in advance in dedicated memory structures within the chip, allowing rapid switching between configurations without lengthy external memory access during the reconfiguration event itself.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The configuration data is divided into multiple segments or blocks that can be independently managed and loaded. The configuration memory is organized into separate banks or regions, allowing parallel loading and selective activation of different configuration segments, thereby reducing overall reconfiguration time.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If configuration data is stored in external memory, then device complexity is reduced, but reconfiguration speed decreases due to memory access time

Engineering Contradiction:
Improveconfiguration storageVSAvoidreconfiguration speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent embeds configuration memory elements directly within the reconfigurable logic blocks and processing elements. The configuration storage is nested inside the functional units that use it, creating a hierarchical structure where configuration data is stored at the same physical location as the logic it configures, eliminating the need for external memory access.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

Dedicated configuration interfaces and control logic act as intermediaries between the configuration memory and the reconfigurable elements. These intermediary structures manage the transfer and application of configuration data efficiently, enabling rapid reconfiguration without direct external memory access while maintaining system organization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12333231B1Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof
Publication Date: 2025.06.17 NEXTSILICON LTD
  • US12333231B1 patent drawing
  • US12333231B1 patent drawing
  • US12333231B1 patent drawing

AI summary

An Integrated Circuit (IC) device, and a method of utilizing thereof, may include: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks. The IC may further include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. The IC may further include a configuration manager circuit, configured to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.