Independent Core and Periphery IC Design Tools
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Solution Overview
Problem
Current FPGA design tools face challenges in efficiently separating and optimizing the design of peripheral and core logic, due to their differing design requirements and compatibility issues across different FPGA versions, leading to complex heuristic problems and difficulties in migration and modification of designs.
Innovation Solution
A system with separate design tools for the core and periphery of an integrated circuit, where one tool defines the functionality of the periphery and the other defines the core, allowing independent optimization and alignment of connections between the two, using interface blocks to manage dependencies and generate configuration information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate design tools are used for core and periphery, then independent optimization and flexibility are improved, but tool integration complexity and interface management increase
Solution Approach 1:
The design system is divided into two independent tools: a first design tool for core logic and a second design tool for periphery logic. Each tool can be optimized independently for its specific domain requirements, with the core tool focusing on general-purpose logic optimization and the periphery tool focusing on protocol-specific optimizations.
Solution Approach 2:
Interface blocks serve as intermediaries between the core and periphery designs. These blocks provide standardized connection points that manage the interfaces between the two separately designed components, reducing the complexity of direct integration while enabling independent optimization of each section.
2Adaptability or versatility
If manual instantiation is combined with behavioral HDL, then design flexibility is improved, but design complexity and time consumption increase
Solution Approach 1:
The design is segmented into periphery components defined through manual instantiation and core logic defined through behavioral HDL. This segmentation allows each part to be developed using the most appropriate method, reducing overall design time while maintaining flexibility.
Solution Approach 2:
The periphery blocks are self-contained with predefined functionality that can be instantiated independently. This self-service approach allows designers to quickly integrate standard periphery functions without manually designing each component, reducing design time while maintaining the ability to customize when needed.
3Manufacturing precision
If periphery blocks are made application-specific, then functional precision is improved, but compatibility across FPGA versions deteriorates
Solution Approach 1:
The periphery design tool provides a library of application-specific blocks that can be instantiated based on the target FPGA version and application requirements. These blocks are designed to be version-agnostic where possible, with the tool automatically adjusting parameters to maintain compatibility across different FPGA versions while preserving functional precision.
Solution Approach 2:
The periphery blocks utilize configurable parameters that can be adjusted based on the target FPGA version. This allows the same block design to maintain high functional precision across different versions by changing implementation parameters rather than redesigning the blocks, thus maintaining both precision and compatibility.
Data Source
AI summary
A system having design tools and methods for using the same in designing an integrated circuit (IC) are described. In one embodiment, an IC design system, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool module configured to determine one or more design specifications for a periphery of the IC, the second tool to function independently of the first tool and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of IC.