IC Data Migration for Power Collapse Retention
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Solution Overview
Problem
Power management in integrated circuits (ICs) faces challenges in reducing energy consumption while preserving data during power collapse events, as resuming computing tasks after a power down is slow and functional data may be lost, especially when using conventional memory types.
Innovation Solution
The integration of a logic block, a memory block, and retention control circuitry that migrates data between retention-relevant storage devices and memory during transitions between operational modes, utilizing both flip-flops and cheaper memory forms to retain data without the area and routing issues of retention flip-flops, and grouping flip-flops by latency sensitivity for efficient data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power is removed from logic block to reduce power consumption, then energy savings are achieved, but functional data is lost
Solution Approach 1:
The patent extracts functional data from the logic block before power collapse and stores it in a separate memory block that remains powered. This separation allows the logic block to be powered down for energy savings while the memory block preserves the functional data, preventing data loss during power collapse events.
Solution Approach 2:
The patent introduces retention control circuitry as an intermediary that manages data migration between the logic block and memory block. This intermediary component coordinates the transfer of functional data before power collapse and restores it afterward, enabling reliable power management without data loss.
2Reliability
If data is migrated to memory block for retention, then data integrity is maintained during power collapse, but area on IC increases
Solution Approach 1:
The patent segments the storage function into two parts: functional data storage in a dedicated memory block and other data in the logic block. This segmentation allows only the necessary functional data to be migrated, minimizing the area required in the memory block while ensuring data integrity during power collapse.
3Reliability
If data migration is implemented, then data retention during power collapse is achieved, but design complexity increases
Solution Approach 1:
The patent merges the data retention function with existing memory infrastructure by utilizing a memory block that can serve both as regular memory and as a retention storage during power collapse. This merging approach reduces design complexity compared to implementing entirely separate retention circuits.
4Use of energy by moving object
If power collapse is used to extend battery life, then energy efficiency improves, but performance resumes slowly
Solution Approach 1:
The patent performs preliminary actions by identifying and migrating only the essential functional data to the memory block before power collapse occurs. This selective preliminary action minimizes the amount of data that needs to be restored afterward, enabling faster performance recovery while maintaining energy efficiency during the power collapse period.
Data Source
AI summary
An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.


