IC System with Debonding Adhesive for Vertical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit systems face challenges in achieving simplified manufacturing processes, smaller dimensions, lower costs, increased functionality, and improved reliability due to limitations in design flexibility and IO connectivity, which are critical for competing in competitive markets and meeting consumer expectations.
Innovation Solution
The development of an integrated circuit system that includes a wafer with a via, a top interconnect, an interconnect pillar, a device interconnect, and a base adhesive that covers the interconnect pillar and device interconnect, providing a non-conductive adhesive for carrier bonding, debonding, and die attachment, which reduces manufacturing costs and enhances reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional integrated circuit packaging methods are used, then manufacturing processes are well-established, but package size is large and manufacturing costs are high
Solution Approach 1:
The patent transitions from planar interconnect arrangements to three-dimensional vertical stacking, utilizing via holes to connect interconnect layers at different heights. This dimensional change enables compact package size while maintaining manufacturing feasibility through sequential layer formation processes
Solution Approach 2:
The patent implements nested interconnect structures where second interconnects are positioned within recesses of first interconnects, and third interconnects are positioned within recesses of second interconnects. This nesting approach maximizes space utilization, reducing package volume while maintaining electrical connectivity through multiple layers
2Adaptability or versatility
If design flexibility is increased to reduce costs and improve functionality, then adaptability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the interconnect system. Conductive materials are used for electrical pathways, insulating materials for isolation, and specific geometric configurations for mechanical support. This localized optimization enables design flexibility while maintaining manufacturability through standardized material and process selection
Solution Approach 2:
The patent forms via holes and prepares substrate surfaces with specific geometries and material coatings before depositing interconnect materials. These preliminary actions establish precise alignment references and bonding surfaces, enabling subsequent interconnect layers to be formed with high precision without requiring ultra-precise positioning during each deposition step
3Adaptability or versatility
If IO connectivity capabilities are increased, then functionality improves, but device complexity increases
Solution Approach 1:
The patent designs interconnect structures that serve multiple functions simultaneously. The same vertical via structures provide both electrical connectivity between layers and mechanical alignment references. Insulating materials provide both electrical isolation and structural support. This multi-functionality increases IO connectivity capabilities while avoiding proportional increases in device complexity
Data Source
AI summary
A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.